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參數(shù)資料
| 型號： | AD7764BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/33頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT S/D 312KSPS 28TSSOP |
| 標準包裝： | 1,000 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 312k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 371mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
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AD7764
Rev. A | Page 22 of 32
AD7764 FUNCTIONALITY
SYNCHRONIZATION
The SYNC input to the AD7764 provides a synchronization
function that allows the user to begin gathering samples of the
analog front-end input from a known point in time.
The SYNC function allows multiple AD7764 devices, operated
from the same master clock that use common SYNC and
RESET signals, to be synchronized so that each ADC
simultaneously updates its output register. Note that all devices
being synchro-nized must operate in the same power mode and
at the same decimation rate.
In the case of a system with multiple AD7764s, connect
common MCLK, SYNC and RESET signals to each AD7764.
The AD7764 SYNC pin is polled by the falling edge of MCLK.
The AD7764 device goes into SYNC when an MCLK falling
edge senses that the SYNC input signal is logic low. At this
point, the digital filter sequencer is reset to 0. The filter is held
in a reset state (in SYNC mode) until the first MCLK falling
edge senses SYNC
Where possible, ensure that all transitions of
to be logic high
SYNC occur
synchronously with the rising edge of MCLK (that is, as far
away as possible from the MCLK falling edge, or decision edge).
Otherwise, abide by the timing specified in Figure 41, which
excludes the SYNC
Keep
rising edge from occurring in a 10 ns
window centered around the MCLK fallings edge.
SYNC logic low for a minimum of four MCLK periods.
When the MCLK falling edge senses that SYNC has returned to
logic high, the AD7764 filters begin to gather input samples
simultaneously. The FSO
06518-
303
MCLK
SYNC
tS MIN
4 ×
tMCLK
tS HOLD
tS SETUP
falling edges are also synchronized,
allowing for simultaneous output of conversion data.
Figure 41. SYNC
Following a
Timing Relative to MCLK
SYNC, the digital filter needs time to settle before
valid data can be read from the AD7764. The user knows there
is valid data on the SDO line by checking the FILTER-SETTLE
status bit (see D7 in Table 9) that is output with each conversion
result. The time from the rising edge of SYNC
OVERRANGE ALERTS
until the FILTER-
SETTLE bit asserts depends on the filter configuration used. See
the Theory of Operation section and the values listed in Table 6
for details on calculating the time until FILTER-SETTLE asserts.
Note that the FILTER_SETTLE bit is designed as a reactionary
flag to indicate when the conversion data output is valid.
The AD7764 offers an overrange function in both a pin and
status bit output. The overrange alerts indicate when the voltage
applied to the AD7764 modulator input pins exceeds the limit
set in the overrange register, indicating that the voltage applied
is approaching a level where the modulator will be overranged.
To set this limit, the user must program the register. The default
overrange limit is set to 80% of the VREF voltage (see the
AD7764 Registers section).
The OVERRANGE pin outputs logic high to alert the user
that the modulator has sampled an input voltage greater in
magnitude than the overrange limit as set in the overrange
register. The OVERRANGE pin is set to logic high when the
modulator samples an input above the overrange limit. After
the input returns below the limit, the OVERRANGE pin returns
to zero. The OVERRANGE pin is updated after the first FIR
filter stage. Its output changes at the ICLK/4 frequency.
The OVR status bit is output as Bit D6 on SDO during a data
conversion and can be checked in the AD7764 status register.
This bit is less dynamic than the OVERRANGE pin output. It is
updated on each conversion result output; that is, the bit changes
at the output data rate. If the modulator has sampled a voltage
input that exceeded the overrange limit during the process of
gathering samples for a particular conversion result output,
then the OVR bit is set to logic high.
O
V
E
RRANG
E
P
IN
O
UT
P
UT
LOGIC
LEVEL
HIGH
LOW
O
V
R
BI
T
LOGIC
LEVEL
HIGH
LOW
OUTPUT FREQUENCY
OF FIR FILTER 1 = ICLK/4
OVERRANGE
LIMIT
OVERRANGE
LIMIT
OBSOLUTE INPUT
TO AD7764
[(VIN+) – (VIN–)]
OUTPUT DATA RATE (ODR)
(ICLK/DECIMATION RATE
t
06518-
016
Figure 42. OVERRANGE Pin and OVR Bit vs. Absolute Voltage
Applied to the Modulator
The output points from FIR Filter 1 in Figure 42 are not drawn
to scale relative to the output data rate points. The FIR Filter 1
output is updated either 16×, 32×, or 64× faster than the output
data rate, depending on the decimation rate in operation.
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| AD7765BRUZ | 功能描述:IC ADC 24BIT S/D 156KSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7765BRUZ-REEL7 | 功能描述:IC ADC 24BIT S/D 156KSPS 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
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