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參數(shù)資料
| 型號： | AD7763BSVZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/33頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT S/D 625KSPS 64-TQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 625k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 955.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-TQFP-EP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，單極；1 個差分，雙極 |
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Data Sheet
AD7763
Rev. B | Page 27 of 32
REGISTERS
The AD7763 has a number of user-programmable registers. The control registers are used to set the decimation rate, the filter configuration,
the low power option, and the control of the differential amplifier. There are also digital gain, offset, and overrange threshold registers.
Writing to these registers involves writing the register address first, followed by a 16-bit data-word. Register addresses, details of
individual bits, and default values are shown here.
CONTROL REGISTER 1—ADDRESS 0X001
Default Value 0x001A
MSB
LSB
DL Filt
RD Ovr
RD Gain
RD Off
RD Stat
0
SYNC
FLEN3
FLEN2
FLEN1
FLEN0
BYP F3
1
DEC2
DEC1
DEC0
Table 17.
Bit
Mnemonic
Comment
15
DL Filt1
Download Filter. Before downloading a user-defined filter, this bit must be set. The filter length bits must also
be set at this time. The write operations that follow are interpreted as the user coefficients for the FIR filter until
all the coefficients and the checksum have been written.
14
RD Ovr1, 2
Read Overrange. If this bit is set, the next read operation outputs the contents of the overrange threshold register
instead of a conversion result.
13
RD Gain1, 2
Read Gain. If this bit is set, the next read operation outputs the contents of the digital gain register.
12
RD Off1, 2
Read Offset. If this bit is set, the next read operation outputs the contents of the digital offset register.
11
RD Stat1, 2
Read Status. If this bit is set, the next read operation outputs the contents of the status register.
10
0
0 must be written to this bit.
9
SYNC1
Synchronize. Setting this bit initiates an internal synchronization routine. Setting this bit simultaneously
on multiple devices synchronizes all filters.
8 to 5
FLEN[3:0]
Filter Length Bits. These bits must be set when the DL Filt bit is set and before a user-defined filter is downloaded.
4
BYP F3
Bypass Filter 3. If this bit is a 0, Filter 3 (programmable FIR) is bypassed.
3
1
1 must be written to this bit.
2 to 0
DEC[2:0]
Decimation Rate. These bits set the decimation rate of Filter 2. Writing a value of 0, 1, or 2 corresponds to
4× decimation. A value of 3 corresponds to 8× decimation; a value of 4 corresponds to 16×; and the
maximum value of 5 corresponds to 32× decimation.
1
Bit 15 to Bit 9 are all self-clearing bits.
2
Only one of these bits can be set in any write operation, because they all determine the contents of the next operation.
CONTROL REGISTER 2—ADDRESS 0X002
Default Value 0x009B
MSB
LSB
0
PD
LPWR
1
D1PD
Table 18.
Bit
Mnemonic
Comment
3
PD
Power Down. Setting this bit powers down the AD7763, reducing the power consumption to 6.35 mW.
2
LPWR
Low Power. If this bit is set, the AD7763 operates in a low power mode. The power consumption is reduced for a 3 dB
reduction in noise performance.
1
1 must be written to this bit.
0
D1PD
Differential Amplifier Power Down. Setting this bit powers down the on-chip differential amplifier.
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