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參數(shù)資料
| 型號： | AD7760BSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 2.5 MSPS, 20-Bit ADC |
| 中文描述： | 1-CH 20-BIT DELTA-SIGMA ADC, PARALLEL ACCESS, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數(shù)： | 9/22頁 |
| 文件大小： | 868K |
| 代理商： | AD7760BSV |
Preliminary Technical Data
AD7760
TQFP Pin
Number
19
20
21
22
25
26
10
Rev. PrN | Page 9 of 22
CSP Pin
Number
13
14
15
16
18
19
8
Pin Mnemonic
Description
V
IN
A1+
V
IN
A1-
V
OUT
A1-
V
OUT
A1+
V
IN
+
V
IN
-
V
REF+
Positive Input to Full-Power Differential Amplifier 1.
Negative Input to Full-Power Differential Amplifier 1.
Negative Output from Full-Power Differential Amplifier 1.
Positive Output from Full-Power Differential Amplifier 1.
Positive Input to the Modulator.
Negative Input to the Modulator.
Reference Input. The input range of this pin is determined by the reference buffer supply
voltage (AV
DD4
). See Reference Section for more details.
Decoupling Pin. A 100nF capacitor must be inserted between this pin and AGND.
Decoupling Pin. A TBD μF capacitor must be inserted between this pin and AGND.
Decoupling Pin. A TBD μF capacitor must be inserted between this pin and AGND.
Bias Current setting pin. A resistor must be inserted between this pin and AGND. For more
details on this, see the Bias Resistor Section.
16-bit bi-directional data bus. These are three-state pins that are controlled by the CS and RD
/WR pins. The operating voltage for these pins is determined by the V
DRIVE
voltage. See
Interfacing Section for more details.
A falling edge on this pin resets all internal digital circuitry. Holding this pin lows keeps the
AD7760 in a reset state.
Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate
will depend on the frequency of this clock. See Clocking Section for more details.
Master Clock ground sensing pin.
Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to
synchronize multiple devices in a system.
Read/Write Input. This pin, in conjunction with the Chip Select pin, is used to read and write
data to and from the AD7760. If this pin is low when CS is low, a read will take place. If this pin
is high and CS is low, a write will occur. See AD7760 Interface Section for more details.
Data Ready Output. Each time that new conversion data is available, an active low pulse,
ICLK period wide, is produced on this pin. See AD7760 Interface Section for further details.
Chip Select Input. Used in conjunction with the RD/WR pin to read and write data to and from
the AD7760. See AD7760 Interface Section for further details.
8
29
30
17
6
21
22
12
DECAP1
DECAP2
DECAP3
R
BIAS
45-52,
54-61
33-48
DB15 – DB0
37
27
RESET
3
3
MCLK
2
36
2
26
MCLK
SYNC
39
29
RD/WR
38
28
DRDY
40
30
CS
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