參數(shù)資料
型號(hào)： AD7739BRU
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 31/32頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 8-CH 24-TSSOP
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 24
采樣率（每秒）： 15.1k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 100mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極
配用： EVAL-AD7739EBZ-ND - BOARD EVAL FOR AD7739
AD7739
Data Sheet
Rev. A | Page 8 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. Pin Configuration (24-Lead TSSOP)
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SCLK
Serial Clock. Schmitt triggered logic input. An external serial clock is applied to this input
to transfer serial data to or from the AD7739.
2
MCLKIN
Master Clock Signal for the ADC. This can be provided in the form of a crystal/resonator or
external clock. A crystal/resonator can be tied across the MCLKIN and MCLKOUT pins.
Alternatively, MCLKIN can be driven with a CMOS compatible clock and MCLKOUT can be
left unconnected.
3
MCLKOUT
Master Clock Signal for the ADC. When the master clock for the device is a crystal/
resonator, the crystal/resonator is connected between MCLKIN and MCLKOUT. If an
external clock is applied to the MCLKIN, MCLKOUT provides an inverted clock signal or
can be switched off to reduce the device power consumption. MCLKOUT can drive one
CMOS load.
4
CS
Chip Select. Active low Schmitt triggered logic input with an internal pull-up resistor.
With this input hardwired low, the AD7739 can operate in its 3-wire interface mode using
SCLK, DIN, and DOUT. CS can be used to select the device in systems with more than one
device on the serial bus. It can also be used as an 8-bit frame synchronization signal.
5
RESET
Schmitt Triggered Logic Input. Active low input that resets the control logic, interface
logic, digital filter, analog modulator, and all on-chip registers of the part to power-on
status. Effectively, everything on the part except the clock oscillator is reset when
the RESET pin is exercised.
6
AVDD
Analog Positive Supply Voltage, 5 V to AGND Nominal.
7
AINCOM/P0
Analog Inputs Common Terminal/Digital Output. The function of this pin is determined
by the P0 DIR bit in the I/O port register; the digital value can be written as the P0 bit in
the I/O port register. The digital voltage is referenced to analog supplies. When
configured as an input (P0 DIR bit set to 1), the single-ended analog inputs 0 to 7
(AIN0 to AIN7) can be referenced to the voltage level of this pin.
8
SYNC/P1
SYNC/Digital Input/Digital Output. The pin direction is determined by the P1 DIR bit; the
digital value can be read/written as the P1 bit in the I/O port register. When the sync bit in
the I/O port register is set to 1, then the SYNC/P1 pin can be used to synchronize the
AD7739 modulator and digital filter with other devices in the system. The digital voltage
is referenced to the analog supplies. When configured as an input, tie the pin high or low.
9 to 16
AIN0 to AIN7
Analog Inputs.
17
REFIN(+)
Positive Terminal of the Differential Reference Input. REFIN(+) voltage potential can lie
anywhere between AVDD and AGND. In normal circuit configuration, connect this pin to a
2.5 V reference voltage.
18
REFIN()
Negative Terminal of the Differential Reference Input. REFIN() voltage potential can lie
anywhere between AVDD and AGND. In normal circuit configuration, connect this pin to a
0 V reference voltage.
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7739
AIN4
AIN5
AIN6
AIN7
SYNC/P1
SCLK
MCLKIN
MCLKOUT
CS
AINCOM/P0
AVDD
RESET
AIN3
AIN2
AIN1
AIN0
REFIN(+)
DGND
DVDD
DIN
DOUT
REFIN(–)
AGND
RDY
03742-0-011
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