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參數(shù)資料
| 型號： | AD7738BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-Channel, High Throughput, |
| 中文描述： | 8-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | MO-153AE, TSSOP-28 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 407K |
| 代理商： | AD7738BRU |
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REV. 0
–4–
AD7738
TIMING SPECIFICATIONS
1, 2, 3
(AV
DD
= 5 V
5%; DV
DD
= 2.7 V to 3.6 V or 5 V 5%; Input Logic 0 = 0 V, Logic 1 = DV
DD
unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comment
MASTER CLOCK RANGE
t
1
t
2
READ OPERATION
t
4
t
54
1
50
500
6.144
MHz
ns
ns
SYNC
Pulsewidth
RESET
Pulsewidth
0
ns
CS
Falling Edge to SCLK Falling Edge Setup Time
SCLK Falling Edge to Data Valid Delay
DV
DD
of 4.75 V to 5.25 V
DV
DD
of 2.7 V to 3.3 V
CS
Falling Edge to Data Valid Delay
DV
DD
of 4.75 V to 5.25 V
DV
DD
of 2.7 V to 3.3 V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge after SCLK Rising Edge Hold Time
Bus Relinquish Time after SCLK Rising Edge
0
0
60
80
ns
ns
t
5A4, 5
0
0
50
50
0
10
60
80
ns
ns
ns
ns
ns
ns
t
6
t
7
t
8
t
96
80
WRITE OPERATION
t
11
t
12
t
13
t
14
t
15
t
16
0
30
25
50
50
0
ns
ns
ns
ns
ns
ns
CS
Falling Edge to SCLK Falling Edge Setup
Data Valid to SCLK Rising Edge Setup Time
Data Valid after SCLK Rising Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS
Rising Edge after SCLK Rising Edge Hold Time
NOTES
1
Sample tested during initial release to ensure compliance.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of 1.6 V.
3
See Figures 1 and 2.
4
These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
5
This specification is relevant only if CS goes low while SCLK is low.
6
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3.
The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing
characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications are subject to change without notice.
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