參數(shù)資料
型號： AD7738BRU
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 8-Channel, High Throughput,
中文描述： 8-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝： MO-153AE, TSSOP-28
文件頁數(shù)： 3/28頁
文件大?。?/td> 407K
代理商： AD7738BRU
REV. 0
AD7738
–3–
Parameter
Min
Typ
Max
Unit
Test Conditions/Comment
LOGIC INPUTS
SCLK, DIN,
CS
, and
RESET
Inputs
Input Current
Input Current
CS
±
1
±
10
–40
μ
A
μ
A
μ
A
pF
V
V
V
V
V
V
CS
= AV
DD
Internal Pull-Up Resistor
Input Capacitance
V
T+
1
V
T–
1
V
T+
– V
T–
1
V
T+
1
V
T–
1
V
T+
– V
T–
1
MCLK IN Only
Input Current
Input Capacitance
V
INL
Input Low Voltage
V
INH
Input High Voltage
V
INL
Input Low Voltage
V
INH
Input High Voltage
4
1.4
0.8
0.3
0.95
0.4
0.3
2
1.4
0.85
2
1.1
0.85
DV
DD
= 5 V
DV
DD
= 5 V
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 3 V
DV
DD
= 3 V
±
10
μ
A
pF
V
V
V
V
4
0.8
DV
DD
= 5 V
DV
DD
= 5 V
DV
DD
= 3 V
DV
DD
= 3 V
3.5
0.4
2.5
LOGIC OUTPUTS
MCLKOUT
10
, DOUT,
RDY
V
OL
Output Low Voltage
V
OH
Output High Voltage
V
OL
Output Low Voltage
V
OH
Output High Voltage
Floating State Leakage Current
Floating State Leakage Capacitance
0.4
V
V
V
V
μ
A
pF
I
SINK
= 800
μ
A, DV
DD
= 5 V
I
SOURCE
= 200
μ
A, DV
DD
= 5 V
I
SINK
= 100
μ
A, DV
DD
= 3 V
I
SOURCE
= 100
μ
A, DV
DD
= 3 V
4.0
0.4
DV
DD
– 0.6
±
1
3
P1 INPUT
Input Current
V
INL
Input Low Voltage
V
INH
Input High Voltage
Levels Referenced to Analog Supplies
±
10
0.8
μ
A
V
V
AV
DD
= 5 V
AV
DD
= 5 V
3.5
P0, P1 OUTPUT
V
OL
Output Low Voltage
0.4
0.4
0.4
V
V
V
V
I
SINK
= 8 mA, T
MAX
= 70
°
C, AV
DD
= 5 V
I
SINK
= 5 mA, T
MAX
= 85
°
C, AV
DD
= 5 V
I
SINK
= 2.5 mA, T
MAX
= 105
°
C, AV
DD
= 5 V
I
SOURCE
= 200
μ
A, AV
DD
= 5 V
V
OH
Output High Voltage
4.0
POWER REQUIREMENTS
AV
DD
– AGND Voltage
DV
DD
– DGND Voltage
4.75
4.75
2.70
5.25
5.25
3.60
16
V
V
V
mA
mA
mA
mA
μ
A
mW
μ
W
AV
DD
Current (Normal Mode)
AV
DD
Current (Internal Buffer Off )
DV
DD
Current (Normal Mode)
11
DV
DD
Current (Normal Mode)
11
AV
DD
+ DV
DD
Current (Standby Mode)
12
Power Dissipation (Normal Mode)
11
Power Dissipation (Standby Mode)
12
13.6
8.5
2.7
1.0
80
85
500
AV
DD
= 5 V
AV
DD
= 5 V
DV
DD
= 5 V
DV
DD
= 3 V
AV
DD
= DV
DD
= 5 V
3
1.5
100
AV
DD
= DV
DD
= 5 V
NOTES
1
Specifications are not production tested, but guaranteed by design and/or characterization data at initial product release.
2
Specifications before calibration. Channel System Calibration reduces these errors to the order of the noise.
3
Applies after the Zero Scale and Full-Scale calibration. The Negative Full Scale error represents the remaining error after removing the offset and gain error.
4
Specifications before calibration. ADC Zero Scale Self-Calibration or Channel Zero Scale System Calibration reduces this error to the order of the noise.
5
The output data span corresponds to the Nominal (Typical) Input Voltage Range. Correct operation of the ADC is guaranteed within the specified min/max.
Outside the Nominal Input Voltage Range, the OVR bit in the Channel Status register is set and the Channel Data register value depends on CLAMP bit in the
Mode register. See the register description and circuit description for more details.
6
If chopping is enabled or when switching between channels, there will be a dynamic current charging the capacitance of the multiplexer, capacitance of the pins,
and any additional capacitance connected to the MUXOUT. See the circuit description for more details.
7
For specified performance. Part is functional with Lower V
8
Dynamic current charging the sigma-delta modulator input switching capacitor.
9
Outside the specified calibration range, calibration is possible but the performance may degrade.
10
These logic output levels apply to the MCLK OUT output when it is loaded with a single CMOS load.
11
With external MCLK, MCLKOUT disabled (CLKDIS bit set in the Mode register).
12
External MCLKIN = 0 V or DV
, Digital Inputs = 0 V or DV
DD
, P0 and P1 = 0 V or AV
DD
.
Specifications are subject to change without notice.
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