TIMING SPECIFICATIONS1, 2, 3 (AVDD
參數(shù)資料
型號(hào): AD7738BRU
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 23/28頁(yè)
文件大小: 0K
描述: IC ADC 24BIT 8-CH 28-TSSOP
標(biāo)準(zhǔn)包裝: 50
位數(shù): 24
采樣率(每秒): 15.4k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 100mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸入數(shù)目和類(lèi)型: 8 個(gè)單端,單極;8 個(gè)單端,雙極;4 個(gè)差分,單極;4 個(gè)差分,雙極
配用: EVAL-AD7738EBZ-ND - BOARD EVAL FOR AD7738
REV. 0
–4–
AD7738
TIMING SPECIFICATIONS1, 2, 3
(AVDD = 5 V
5%; DVDD = 2.7 V to 3.6 V or 5 V
5%; Input Logic 0 = 0 V, Logic 1 = DVDD unless otherwise noted.)
Parameter
Min
Typ
Max
Unit
Test Conditions/Comment
MASTER CLOCK RANGE
1
6.144
MHz
t1
50
ns
SYNC Pulsewidth
t2
500
ns
RESET Pulsewidth
READ OPERATION
t4
0ns
CS Falling Edge to SCLK Falling Edge Setup Time
t5
4
SCLK Falling Edge to Data Valid Delay
060
ns
DVDD of 4.75 V to 5.25 V
080
ns
DVDD of 2.7 V to 3.3 V
t5A
4, 5
CS Falling Edge to Data Valid Delay
060
ns
DVDD of 4.75 V to 5.25 V
080
ns
DVDD of 2.7 V to 3.3 V
t6
50
ns
SCLK High Pulsewidth
t7
50
ns
SCLK Low Pulsewidth
t8
0ns
CS Rising Edge after SCLK Rising Edge Hold Time
t9
6
10
80
ns
Bus Relinquish Time after SCLK Rising Edge
WRITE OPERATION
t11
0ns
CS Falling Edge to SCLK Falling Edge Setup
t12
30
ns
Data Valid to SCLK Rising Edge Setup Time
t13
25
ns
Data Valid after SCLK Rising Edge Hold Time
t14
50
ns
SCLK High Pulsewidth
t15
50
ns
SCLK Low Pulsewidth
t16
0ns
CS Rising Edge after SCLK Rising Edge Hold Time
NOTES
1Sample tested during initial release to ensure compliance.
2All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD) and timed from a voltage level of 1.6 V.
3See Figures 1 and 2.
4These numbers are measured with the load circuit of Figure 3 and defined as the time required for the output to cross the V
OL or VOH limits.
5This specification is relevant only if CS goes low while SCLK is low.
6These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 3.
The measured number is then extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing
characteristics are the true bus relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications are subject to change without notice.
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