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| 型號： | AD7730BRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/53頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC BRDGE TRANSDCR 24SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 24 |
| 通道數(shù)： | 1 |
| 功率（瓦特）： | 125mW |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 5.25 V |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | AD7730BRZ-REEL7DKR |
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AD7730/AD7730L
–27–
Chop Mode
With chop mode enabled on the AD7730, the signal processing
chain is synchronously chopped at the analog input and at the
output of the first stage filter. This means that for each output
of the first stage filter to be computed, the full settling time of
the filter has to elapse. This results in an output rate from the
filter that is three times lower than for a given SF word than for
nonchop mode. The output update and first notch of this first
stage filter correspond and are determined by the relationship:
Output Rate
=
f CLK IN
16
×
1
3
× SF
where SF is the decimal equivalent of the data loaded to the SF
bits of the Filter Register and fCLK IN is the master clock frequency.
Second Stage Filter
As stated earlier, the second stage filter has three distinct modes
of operation which result in a different overall filter profile for
the part. The modes of operation of the second stage filter are
discussed in the following sections along with the different filter
profiles which result.
Normal FIR Operation
The normal mode of operation of the second stage filter is as a
22-tap low-pass FIR filter. This second stage filter processes the
output of the first stage filter and the net frequency response of
the filter is simply a product of the filter response of both filters.
The overall filter response of the AD7730 is guaranteed to have
no overshoot.
Figure 11 shows the full frequency response of the AD7730 when
the second stage filter is set for normal FIR operation. This
response is for chop mode enabled with the decimal equivalent
of the word in the SF bits set to 512 and a master clock frequency
of 4.9152 MHz. The response will scale proportionately with
master clock frequency. The response is shown from dc to
100 Hz. The rejection at 50 Hz
±1 Hz and 60 Hz ± 1 Hz is
better than 88 dB.
The –3 dB frequency for the frequency response of the AD7730
with the second stage filter set for normal FIR operation and
chop mode enabled is determined by the following relationship:
f 3dB = 0.0395 ×
f CLK IN
16
×
1
3
× SF
In this case, f3 dB = 7.9 Hz and the stopband, where the attenua-
tion is greater than 64.5 dB, is determined by:
f STOP = 0.14 ×
f CLK IN
16
×
1
3
× SF
In this case, fSTOP = 28 Hz.
FREQUENCY – Hz
0
–60
–100
090
GAIN
–
dB
10
20
30
40
50
60
70
80
–10
–50
–70
–90
–30
–40
–80
–20
–120
–110
100
Figure 11. Detailed Full Frequency Response of AD7730
(Second Stage Filter as Normal FIR, Chop Enabled)
Figure 12 shows the frequency response for the same set of
conditions as for Figure 11, but in this case the response is
shown out to 600 Hz. This response shows that the attenuation
of input frequencies close to 200 Hz and 400 Hz is significantly
less than at other input frequencies. These “peaks” in the fre-
quency response are a by-product of the chopping of the input.
The plot of Figure 12 is the amplitude for different input fre-
quencies. Note that because the output rate is 200 Hz for the
conditions under which Figure 12 is plotted, if something ex-
isted in the input frequency domain at 200 Hz, it would be
aliased and appear in the output frequency domain at dc.
FREQUENCY – Hz
0
–60
–100
0
450
GAIN
–
dB
50
100 150 200 250 300 350 400
–10
–50
–70
–90
–30
–40
–80
–20
–120
–110
500 550
600
Figure 12. Expanded Full Frequency Response of AD7730
(Second Stage Filter as Normal FIR, Chop Enabled)
REV. B
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參數(shù)描述 |
|---|---|
| AD7730L | 制造商:AD 制造商全稱:Analog Devices 功能描述:Bridge Transducer ADC |
| AD7730LBR | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 600sps 24-bit Serial 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 0.6KSPS 24BIT SERL 24SOIC W - Tape and Reel |
| AD7730LBR-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730LBRU | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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