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| 型號： | AD7718BR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 8-/10-Channel, Low Voltage, Low Power, ADCs |
| 中文描述： | 10-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封裝： | PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 35/44頁 |
| 文件大?。?/td> | 339K |
| 代理商： | AD7718BR |
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REV. 0
AD7708/AD7718
–35–
AD7708/AD7718 to 68HC11 Interface
Figure 19 shows an interface between the AD7708/AD7718 and
the 68HC11 microcontroller. The diagram shows the minimum
(3-wire) interface with
CS
on the AD7708/AD7718 hardwired
low. In this scheme, the RDY bit of the Status Register is
monitored to determine when the Data Register is updated.
An alternative scheme, which increases the number of inter-
face lines to four, is to monitor the
RDY
output line from the
AD7708/AD7718. The monitoring of the
RDY
line can be done
in two ways. First,
RDY
can be connected to one of the 68HC11’s
port bits (such as PC0), which is configured as an input. This
port bit is then polled to determine the status of
RDY
. The
second scheme is to use an interrupt driven system, in which
case the
RDY
output is connected to the IRQ input of the
68HC11. For interfaces that require control of the
CS
input on
the AD7708/AD7718, one of the port bits of the 68HC11 (such
as PC1), which is configured as an output, can be used to drive
the
CS
input.
68HC11
V
DD
SS
SCK
MISO
MOSI
RESET
SCLK
CS
DIN
DOUT
V
DD
AD7708/
AD7718
Figure 19. AD7708/AD7718-to-68HC11 Interface
The 68HC11 is configured in the master mode with its CPOL
bit set to a Logic 1 and its CPHA bit set to a Logic 1. When the
68HC11 is configured like this, its SCLK line idles high between
data transfers. The AD7708/AD7718 is not capable of full duplex
operation. If the AD7708/AD7718 is configured for a write
operation, no data appears on the DOUT lines even when the
SCLK input is active. Similarly, if the AD7708/AD7718 is config-
ured for a read operation, data presented to the part on the DIN
line is ignored even when SCLK is active.
AD7708/AD7718-to-8051 Interface
An interface circuit between the AD7708/AD7718 and the
8XC51 microcontroller is shown in Figure 20. The diagram
shows the minimum number of interface connections with
CS
on the AD7708/AD7718 hardwired low. In the case of the
8XC51 interface the minimum number of interconnects is just
two. In this scheme, the RDY bit of the Status Register is
monitored to determine when the Data Register is updated. The
alternative scheme, which increases the number of interface
lines to three, is to monitor the
RDY
output line from the
AD7708/AD7718. The monitoring of the
RDY
line can be done
in two ways. First,
RDY
can be connected to one of the 8XC51’s
port bits (such as P1.0) which is configured as an input. This
port bit is then polled to determine the status of
RDY
. The
second scheme is to use an interrupt-driven system, in which
case the
RDY
output is connected to the INT1 input of the
8XC51. For interfaces that require control of the
CS
input on
the AD7708/AD7718, one of the port bits of the 8XC51 (such
as P1.1), which is configured as an output, can be used to drive
the
CS
input. The 8XC51 is configured in its Mode 0 serial
interface mode. Its serial interface contains a single data line. As
a result, the DOUT and DIN pins of the AD7708/AD7718 should
be connected together with a 10 k
pull-up resistor. The serial
clock on the 8XC51 idles high between data transfers. The
8XC51 outputs the LSB first in a write operation, while the
AD7708/AD7718 expects the MSB first so the data to be trans-
mitted has to be rearranged before being written to the output
serial register. Similarly, the AD7708/AD7718 outputs the MSB
first during a read operation while the 8XC51 expects the LSB
first. Therefore, the data read into the serial buffer needs to be
rearranged before the correct data word from the AD7708/
AD7718 is available in the accumulator.
DV
DD
8XC51
AD7708/
AD7718
P3.0
P3.1
RESET
SCLK
CS
DIN
DOUT
DV
DD
10k
Figure 20. AD7708/AD7718-to-8XC51 Interface
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