參數(shù)資料
型號(hào)： AD7718BR
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 8-/10-Channel, Low Voltage, Low Power, ADCs
中文描述： 10-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝： PLASTIC, SOIC-28
文件頁(yè)數(shù)： 22/44頁(yè)
文件大?。?/td> 339K
代理商： AD7718BR
REV. 0
–22–
AD7708/AD7718
ON-CHIP REGISTERS
The AD7708 and AD7718 are controlled and configured via
a number of on-chip registers which are shown in Figure 15.
The first of these registers is the communications register
which is used to control all operations on these converters. All
communications with these parts must start with a write to
the communications register to specify the next operation to
be performed. After a power-on or RESET, the device defaults
to waiting for a write to the communications register. The
STATUS register contains information pertaining to the operat-
ing conditions of the converter. The STATUS register is a read
only register. The MODE register is used to configure the con-
version mode, calibration, chop enable/disable, reference select,
channel configuration and buffered or unbuffered operation on
the AINCOM analog input. The MODE register is a read/write
register. The ADC Control register is a read/write register used
to select the active channel and program its input range and
bipolar/unipolar operation. The I/O control register is a read/
write register used to configure the operation of the 2-pin I/O
port. The filter register is a read/write register used to program
the data update rate of the converter. The ADC Data register is
a read only register that contains the result of a data conversion
on the selected channel. The ADC offset registers are read/write
registers that contain the offset calibration data. There are five
offset registers, one for each of the fully differential input channels.
When configured for pseudo-differential input mode the chan-
nels share offset registers. The ADC gain registers are read/write
registers that contain the gain calibration data. There are five
ADC gain registers, one for each of the fully differential input
channels. When configured for pseudo differential input mode
the channels share gain registers. The ADC contains Test registers
for factory use only, the user is advised not to alter the oper-
ating conditions of these registers. The ID register is a read only
register and is used for silicon identification purposes. The follow-
ing sections contains more in-depth detail on all of these registers.
In the following descriptions,
SET
implies a Logic 1 state and
CLEARED
implies a Logic 0 state unless otherwise stated.
DOUT
DOUT
DOUT
DIN
DOUT
DIN
DOUT
DIN
DOUT
DIN
DOUT
DOUT
DIN
DOUT
DOUT
WEN
R/
W
0
0
A1
A2
A3
A0
COMMUNICATIONS REGISTER
DOUT
DIN
DIN
REGISTER
SELECT
DECODER
ADC DATA REGISTER
STATUS REGISTER
MODE REGISTER
ADC CONTROL REGISTER
I/O CONTROL REGISTER
FILTER REGISTER
ID REGISTER
TEST REGISTER
ADC GAIN REGISTER
ADC OFFSET REGISTER
DIN
DIN
Figure 15. On-Chip Registers
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