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參數(shù)資料
| 型號(hào)： | AD7716 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 22-Bit Data Acquisition System(LC2MOS 22位數(shù)據(jù)采集系統(tǒng)) |
| 中文描述： | 22位數(shù)據(jù)采集系統(tǒng)（LC2MOS 22位數(shù)據(jù)采集系統(tǒng)） |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 439K |
| 代理商： | AD7716 |
REV. A
AD7716
–10–
relationship between input bandwidth and settling is given in
Table I. Because of this settling time, most sigma delta ADCs
are unsuitable for high speed multiplexing, where channels are
switched and converted sequentially at high rates, as switching
between channels can cause a step change in the input. How-
ever, the AD7716 is a sigma-delta solution to multichannel ap-
plications, since it can process four channels simultaneously. In
addition, it is easy to cascade several devices in order to increase
the number of channels being processed.
Figure 6. Frequency Response of AD7716 Filter
Figure 6 shows the filter frequency response for a cutoff fre-
quency of 73 Hz. This is a (sinx/x)
3
response (also called sinc
3
)
that provides greater than 100 dB rejection at the notch fre-
quencies. The relationship between the programmed cutoff
frequency and the first notch is constant (f
NOTCH
= 3.81
3
f
CUTOFF
). The first notch frequency is also the output data rate.
The settling time to a full-scale step input is four times the out-
put data period. Programming a different cutoff frequency via
FC0–FC2 does not alter the profile of the filter response, it sim-
ply changes the frequency of the notches.
In Figure 6, the first notch is at 278 Hz. This is also the output
data rate. Settling time to a full-scale step input is 10.8 ms.
The digital filter can be defined by the following equations.
H
(
z
)
=
1
N
×
1–
Z
–
N
1–
Z
–1
3
H
(
f
)
=
sin
π
f
/
f
S
)
π
f
/
f
S
)
3
where
N
= Ratio of Modulator Sampling Frequency to Output
Rate
and
f
S
= Output Rate.
Post Filtering
In the AD7716, the on-chip modulator provides the digital filter
with samples at a rate of 570 kHz. The filter decimates these
samples to provide data at an output rate which corresponds to
the programmed first notch frequency of the filter.
If the user wants to reduce the output noise from the device for
bandwidths less than 36.5 Hz, then it is possible to employ extra
filtering after the AD7716. This extra digital filtering is called
post filtering. If a straight averaging filter is used, for example, a
reduction in bandwidth by a factor of 2 results in
√
2
reduction
in the rms noise. This additional filtering will also result in a
longer settling time.
Antialias Considerations
The digital filter does not provide any rejection at integer mul-
tiples of the modulator sampling frequency (n
3
570 kHz,
where n = 1, 2, 3, . . .). This means that there are frequency
bands,
±
f
3dB
wide (f
3dB
is the cutoff frequency selected by FC0
to FC2) where noise passes unattenuated to the output. How-
ever, due to the AD7716’s high oversampling ratio, these bands
occupy only a small fraction of the spectrum and most broad-
band noise is filtered.
In spectral analysis applications, it is important to note that at-
tenuation at half the output update rate is 16 dB. Extra front-
end filtering or post filtering may be required to keep aliases in
this frequency band at an acceptable level.
USING THE AD7716
SYSTEM DESIGN CONSIDERATIONS
The AD7716 operates differently from successive approxima-
tion ADCs or other integrating ADCs. Since it samples the sig-
nal continuously, like a tracking ADC, there is no need for a
start convert command. The output register is updated at a rate
dependent on the programmed cutoff frequency, and the output
can be read at any time.
Input Signal Conditioning
The input range for the AD7716 is
±
V
REF
, where V
REF
= 2.5 V
±
10%. Other input ranges can be accommodated by input sig-
nal conditioning. This may take the form of gain to increase a
smaller signal range, or passive attenuation to reduce a larger in-
put voltage range.
–240
1668
73
0
0
–180
–220
–200
–120
–160
–140
–100
–80
–60
–20
–40
1390
1112
834
556
FREQUENCY – Hz
278
G
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