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參數(shù)資料
| 型號(hào)： | AD7712EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LC 2 MOS Signal Conditioning ADC(229.08 k) |
| 中文描述： | 立法會(huì)二馬鞍山信號(hào)調(diào)理模數(shù)轉(zhuǎn)換器（229.08十一） |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 229K |
| 代理商： | AD7712EB |
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2
–17–
REV. E
AD7712
The current drawn from the DV
DD
power supply is also directly
related to f
CLK IN
. Reducing f
CLK IN
by a factor of two will halve
the DV
DD
current but will not affect the current drawn from the
AV
DD
power supply.
System Synchronization
If multiple AD7712s are operated from a common master clock,
they can be synchronized to update their output registers simul-
taneously. A falling edge on the
SYNC
input resets the filter
and places the AD7712 into a consistent, known state. A com-
mon signal to the AD7712s’
SYNC
inputs will synchronize their
operation. This would normally be done after each AD7712 has
performed its own calibration or has had calibration coefficients
loaded to it.
The
SYNC
input can also be used to reset the digital filter in
systems where the turn-on time of the digital power supply
(DV
DD
) is very long. In such cases, the AD7712 will start oper-
ating internally before the DV
DD
line has reached its minimum
operating level, +4.75 V. With a low DV
DD
voltage, the
AD7712’s internal digital filter logic does not operate correctly.
Thus, the AD7712 may have clocked itself into an incorrect
operating condition by the time that DV
DD
has reached its cor-
rect level. The digital filter will be reset upon issue of a calibra-
tion command (whether it is self-calibration, system calibration
or background calibration) to the AD7712. This ensures correct
operation of the AD7712. In systems where the power-on de-
fault conditions of the AD7712 are acceptable, and no calibra-
tion is performed after power-on, issuing a
SYNC
pulse to the
AD7712 will reset the AD7712’s digital filter logic. An R, C on
the
SYNC
line, with R, C time constant longer than the DV
DD
power-on time, will perform the
SYNC
function.
Accuracy
Sigma-delta ADCs, like VFCs and other integrating ADCs, do
not contain any source of nonmonotonicity and inherently offer
no missing codes performance. The AD7712 achieves excellent
linearity by the use of high quality, on-chip silicon dioxide ca-
pacitors, which have a very low capacitance/voltage coefficient.
The device also achieves low input drift through the use of
chopper stabilized techniques in its input stage. To ensure
excellent performance over time and temperature, the AD7712
uses digital calibration techniques that minimize offset and gain
error.
Autocalibration
Autocalibration on the AD7712 removes offset and gain errors
from the device. A calibration routine should be initiated on the
device whenever there is a change in the ambient operating
temperature or supply voltage. It should also be initiated if there
is a change in the selected gain, filter notch or bipolar/unipolar
input range. However, if the AD7712 is in its background cali-
bration mode, the above changes are all automatically taken care
of (after the settling time of the filter has been allowed for).
The AD7712 offers self-calibration, system calibration and
background calibration facilities. For calibration to occur on the
selected channel, the on-chip microcontroller must record the
modulator output for two different input conditions. These are
“zero-scale” and “full-scale” points. With these readings, the
microcontroller can calculate the gain slope for the input to
output transfer function of the converter. Internally, the part
works with a resolution of 33 bits to determine its conversion
result of either 16 bits or 24 bits.
V
BIAS
Input
The V
BIAS
input determines at what voltage the internal analog
circuitry is biased. It essentially provides the return path for
analog currents flowing in the modulator, and as such it should
be driven from a low impedance point to minimize errors.
For maximum internal headroom, the V
BIAS
voltage should be
set halfway between AV
DD
and V
SS
. The difference between
AV
DD
and (V
BIAS
+ 0.85
×
V
REF
) determines the amount of
headroom the circuit has at the upper end, while the difference
between V
SS
and (V
BIAS
– 0.85
×
V
REF
) determines the amount
of headroom the circuit has at the lower end. Care should be
taken in choosing a V
BIAS
voltage to ensure that it stays within
prescribed limits. For single +5 V operation, the selected V
BIAS
voltage must ensure that V
BIAS
±
0.85
×
V
REF
does not exceed
AV
DD
or V
SS
or that the V
BIAS
voltage itself is greater than V
SS
+ 2.1 V and less than AV
DD
– 2.1 V. For single +10 V operation
or dual
±
5 V operation, the selected V
BIAS
voltage must ensure
that V
BIAS
±
0.85
×
V
REF
does not exceed AV
DD
or V
SS
or that
the V
BIAS
voltage itself is greater than V
SS
+ 3 V or less than
AV
DD
– 3 V. For example, with AV
DD
= +4.75 V, V
SS
= 0 V
and V
REF
= +2.5 V, the allowable range for the V
BIAS
voltage is
+2.125 V to +2.625 V. With AV
DD
= +9.5 V, V
SS
= 0 V and
V
REF
= +5 V, the range for V
BIAS
is +4.25 V to +5.25 V. With
AV
DD
= +4.75 V, V
SS
= –4.75 V and V
REF
= +2.5 V, the V
BIAS
range is –2.625 V to +2.625 V.
The V
BIAS
voltage does have an effect on the AV
DD
power sup-
ply rejection performance of the AD7712. If the V
BIAS
voltage
tracks the AV
DD
supply, it improves the power supply rejection
from the AV
DD
supply line from 80 dB to 95 dB. Using an ex-
ternal Zener diode, connected between the AV
DD
line and V
BIAS,
as the source for the V
BIAS
voltage gives the improvement in
AV
DD
power supply rejection performance.
USING THE AD7712
SYSTEM DESIGN CONSIDERATIONS
The AD7712 operates differently from successive approximation
ADCs or integrating ADCs. Since it samples the signal continu-
ously, like a tracking ADC, there is no need for a start convert
command. The output register is updated at a rate determined
by the first notch of the filter and the output can be read at any
time, either synchronously or asynchronously.
Clocking
The AD7712 requires a master clock input, which may be an
external TTL/CMOS compatible clock signal applied to the
MCLK IN pin with the MCLK OUT pin left unconnected.
Alternatively, a crystal of the correct frequency can be con-
nected between MCLK IN and MCLK OUT, in which case the
clock circuit will function as a crystal controlled oscillator. For
lower clock frequencies, a ceramic resonator may be used in-
stead of the crystal. For these lower frequency oscillators, exter-
nal capacitors may be required on either the ceramic resonator
or on the crystal.
The input sampling frequency, the modulator sampling fre-
quency, the –3 dB frequency, output update rate and calibration
time are all directly related to the master clock frequency,
f
CLK IN.
Reducing the master clock frequency by a factor of two
will halve the above frequencies and update rate and will double
the calibration time.
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