參數(shù)資料
型號(hào)： AD7712AN
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： LC2MOS Signal Conditioning ADC
中文描述： 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24
封裝： 0.300 INCH, PLASTIC, DIP-24
文件頁(yè)數(shù)： 22/28頁(yè)
文件大?。?/td> 229K
代理商： AD7712AN
REV. E
–22–
AD7712
Figure 13a shows a read operation from the AD7712 where
RFS
remains low for the duration of the data word transmission.
With
DRDY
low, the
RFS
input is brought low. The input
SCLK signal should be low between read and write operations.
RFS
going low places the MSB of the word to be read on the
serial data line. All subsequent data bits are clocked out on a
high to low transition of the serial clock and are valid prior to
the following rising edge of this clock. The penultimate falling
edge of SCLK clocks out the LSB and the final falling edge
resets the
DRDY
line high. This rising edge of
DRDY
turns off
the serial data output.
Figure 13b shows a timing diagram for a read operation where
RFS
returns high during the transmission of the word and re-
turns low again to access the rest of the data word. Timing
parameters and functions are very similar to that outlined for
Figure 13a, but Figure 13b has a number of additional times to
show timing relationships when
RFS
returns high in the middle
of transferring a word.
RFS
should return high during a low time of SCLK. On the
rising edge of
RFS
, the SDATA output is turned off.
DRDY
remains low and will remain low until all bits of the data word
are read from the AD7712, regardless of the number of times
RFS
changes state during the read operation. Depending on the
time between the falling edge of SCLK and the rising edge of
RFS
, the next bit (BIT N + 1) may appear on the databus be-
fore
RFS
goes high. When
RFS
returns low again, it activates
the SDATA output. When the entire word is transmitted, the
DRDY
line will go high, turning off the SDATA output as per
Figure 13a.
RFS
(I)
SCLK (I)
SDATA (O)
LSB
MSB
THREE-STATE
A0 (I)
DRDY
(O)
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
Figure 13a. External Clocking Mode, Output Data Read Operation
THREE-STATE
MSB
BIT N
BIT N+1
SDATA (O)
SCLK (I)
RFS
(I)
A0 (I)
DRDY
(O)
t
20
t
22
t
26
t
24
t
25
t
27
t
31
t
24
t
25
t
30
Figure 13b. External Clocking Mode, Output Data Read Operation (
RFS
Returns High During Read Operation)
相關(guān)PDF資料
PDF描述
AD7712AQ LC2MOS Signal Conditioning ADC
AD7712AR LC2MOS Signal Conditioning ADC
AD7712SQ LC2MOS Signal Conditioning ADC
AD7712* Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block; Package: SSOP; No of Pins: 16; Temperature Range: 0°C to +70°C
AD7712 Signal Conditioning ADC(LC2MOS信號(hào)調(diào)節(jié)A/D轉(zhuǎn)換器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7712ANZ 功能描述:IC ADC SIGNAL COND LC2MOS 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
AD7712ANZ 制造商:Analog Devices 功能描述:IC ADC 24-BIT SIGMA DELTA
AD7712AQ 制造商:Rochester Electronics LLC 功能描述:24 BIT SIGMA DELTA ADC IC - Bulk
AD7712AR 功能描述:IC ADC SIGNAL COND LC2MOS 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個(gè)單端，雙極
AD7712AR-REEL 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 1.028ksps 24-bit Serial 24-Pin SOIC W T/R 制造商:Analog Devices 功能描述:ADC SGL DELTA-SIGMA 1.028KSPS 24BIT SERL 24SOIC W - Tape and Reel
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*