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參數(shù)資料
| 型號： | AD7711AN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | LC2MOS Signal Conditioning ADC with RTD Excitation Currents |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDIP24 |
| 封裝： | 0.300 INCH, PLASTIC, MO-095AG, DIP-24 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 242K |
| 代理商： | AD7711AN |
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REV. F
–22–
AD7711
Figures 12a and 12b show timing diagrams for reading from the
AD7711 in the external clocking mode. Figure 12a shows a
situation where all the data is read from the AD7711 in one read
operation. Figure 12b shows a situation where the data is read
from the AD7711 over a number of read operations. Both read
operations show a read from the AD7711’s output data register.
A read from the control register or calibration registers is similar
but in these cases the
DRDY
line is not related to the read func-
tion. Depending on the output update rate, it can go low at any
stage in the control/calibration register read cycle without affect-
ing the read and its status should be ignored. A read operation
from either the control or calibration registers must always read
24 bits of data from the respective register.
Figure 12a shows a read operation from the AD7711 where
RFS
remains low for the duration of the data word transmission.
With
DRDY
low, the
RFS
input is brought low. The input
SCLK signal should be low between read and write operations.
RFS
going low places the MSB of the word to be read on the
serial data line. All subsequent data bits are clocked out on a
high to low transition of the serial clock and are valid prior to
the following rising edge of this clock. The penultimate falling
edge of SCLK clocks out the LSB and the final falling edge
resets the
DRDY
line high. This rising edge of
DRDY
turns off
the serial data output.
Figure 12b shows a timing diagram for a read operation where
RFS
returns high during the transmission of the word and
returns low again to access the rest of the data word. Timing
parameters and functions are very similar to that outlined for
Figure 12a but Figure 12b has a number of additional times to
show timing relationships when
RFS
returns high in the middle
of transferring a word.
RFS
should return high during a low time of SCLK. On the
rising edge of
RFS
, the SDATA output is turned off.
DRDY
remains low and will remain low until all bits of the data word
are read from the AD7711, regardless of the number of times
RFS
changes state during the read operation. Depending on the
time between the falling edge of SCLK and the rising edge of
RFS
, the next bit (BIT N+1) may appear on the databus before
RFS
goes high. When
RFS
returns low again, it activates the
SDATA output. When the entire word is transmitted, the
DRDY
line will go high turning off the SDATA output as per
Figure 12a.
t
20
SDATA (O)
SCLK (I)
RFS
(I)
A0 (I)
DRDY
(O)
t
22
t
24
t
25
t
26
t
27
t
29
t
28
t
23
t
21
THREE-STATE
MSB
LSB
Figure 12a. External-Clocking Mode, Output Data Read Operation
t
20
SDATA (O)
SCLK (I)
RFS
(I)
A0 (I)
DRDY
(O)
t
22
t
24
t
25
t
26
t
27
t
24
t
25
THREE-STATE
MSB
t
30
t
31
BIT N
BIT N+1
Figure 12b. External-Clocking Mode, Output Data Read Operation (
RFS
Returns High During Read Operation)
相關PDF資料 |
PDF描述 |
|---|---|
| AD7711AQ | LC2MOS Signal Conditioning ADC with RTD Excitation Currents |
| AD7711AR | LC2MOS Signal Conditioning ADC with RTD Excitation Currents |
| AD7711SQ | LC2MOS Signal Conditioning ADC with RTD Excitation Currents |
| AD7711* | LC2MOS Signal Conditioning ADC with RTD Excitation Currents |
| AD7711A | Signal Conditioning ADC with RTD Current Source(帶RTD電流源信號調(diào)節(jié)A/D轉(zhuǎn)換器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7711ANZ | 功能描述:IC ADC 24BIT RTD I SOURCE 24-DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關文件:TSA1204 View All Specifications 標準包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應商設備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個單端，單極；2 個差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
| AD7711ANZ | 制造商:Analog Devices 功能描述:IC ADC 24-BIT SIGMA DELTA |
| AD7711AQ | 功能描述:IC ADC 24BIT RTD I SOURCE 24CDIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7711AR | 功能描述:IC ADC 24BIT RTD I SOURCE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7711AR-REEL | 功能描述:IC ADC 24BIT RTD I SOURCE 24SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
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