參數(shù)資料
型號(hào)： AD7709ARU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/32頁(yè)
文件大小： 0K
描述： IC ADC 16BIT SIGMA-DELTA 24TSSOP
產(chǎn)品變化通告： Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 62
位數(shù)： 16
采樣率（每秒）： 105
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 3.75mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸入數(shù)目和類型： 2 個(gè)差分，單極；2 個(gè)差分，雙極；4 個(gè)偽差分，單極；4 個(gè)偽差分，雙極
REV. A
AD7709
–17–
Bit
Location
Name
Description
CONFIG16
I1EN0
IEXC1 Current Source Enable Bit
CONFIG15
P4DIG
Digital Input Enable.
Set by user to enable pin AIN4/P4 as a digital input. A weak pull-up resistor is activated in this state.
Cleared by user to configure pin AIN4/P4 as an analog input.
CONFIG14
P3DIG
Digital Input Enable.
Set by user to enable pin AIN3/P3 as a digital input. A weak pull-up resistor is activated in this state.
Cleared by user to configure pin AIN3/P3 as an analog input.
CONFIG13
P2EN
SW2/P2 Digital Output Enable Bit.
Set by user to enable P2 as a regular digital output pin.
Cleared by user to three-state the P2 output. PSW2 takes precedence over P2EN.
CONFIG12
P1EN
SW1/P1 Digital Output Enable Bit.
Set by user to enable P1 as a regular digital output pin.
Cleared by user to three-state the P1 output. PSW1 takes precedence over P1EN.
CONFIG11
P4DAT
Digital Input Port Data Bit.
P4DAT is read only and will return a zero if P4DIG equals zero.
If P4 is enabled as a digital input, the readback value indicates the status of pin P4.
CONFIG10
P3DAT
Digital Input Port Data Bit.
P3DAT is read only and will return a zero if P3DIG equals zero.
If P3 is enabled as a digital input, the readback value indicates the status of pin P3.
CONFIG9
P2DAT
Digital Output Port Data Bit. P2 is a digital output only. When the port is active as an output (P2EN = 1),
the value written to this data bit appears at the output port. Reading P2DAT will return the last value
written to the P2DAT bit.
CONFIG8
P1DAT
Digital Output Port Data Bit. P1 is a digital output only. When the port is active as an output (P1EN = 1),
the value written to this data bit appears at the output port. Reading P1DAT will return the last value
written to the P1DAT bit.
CONFIG7
REFSEL
ADC Reference Input Select.
Cleared by the user to select REFIN1(+) and REFIN1(–) as the ADC reference.
Set by the user to select REFIN2(+) and REFIN2(–) as the ADC reference.
CONFIG6
CH2
ADC Input Channel Selection Bit. It is used in conjunction with CH1 and CH0 as shown below.
CONFIG5
CH1
ADC Input Channel Selection Bit. It is used in conjunction with CH2 and CH0 as shown below.
CONFIG4
CH0
ADC Input Channel Selection Bit. It is used in conjunction with CH2 and CH1 as shown below.
The Buffer column indicates if the analog inputs are buffered or unbuffered. This determines the common-mode input range
on each input. If the input is unbuffered (AINCOM), the common-mode input includes ground.
Table VII. Configuration Register Bit Designations (continued)
CH2 CH1
CH0
Positive Input
Negative Input
Buffer
0
00
AIN1
AINCOM
Positive Analog Input
0
01
AIN2
AINCOM
Positive Analog Input
0
10
AIN3
AINCOM
Positive Analog Input
0
11
AIN4
AINCOM
Positive Analog Input
1
00
AIN1
AIN2
Positive and Negative Analog Inputs
1
01
AIN3
AIN4
Positive and Negative Analog Inputs
1
10
AINCOM
None
1
11
AIN2
Positive and Negative Analog Inputs
I1EN1
I1EN0
Function
00
IEXC1 Current Source OFF
01
IEXC1 Current Source Routed to the IOUT1 Pin
10
IEXC1 Current Source Routed to the IOUT2 Pin
11
Reserved
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