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參數(shù)資料
| 型號： | AD7707EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 3 V/5 V 610 V Input Range 1 mW 3-Channel 16-Bit Sigma-Delta ADC(316.51 k) |
| 中文描述： | 3伏/ 5伏610 V輸入范圍1毫瓦3通道16位Σ-Δ模數(shù)轉(zhuǎn)換器（316.51十一） |
| 文件頁數(shù)： | 25/40頁 |
| 文件大小： | 316K |
| 代理商： | AD7707EB |
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REV. A
AD7707
–25–
MCLK IN
MCLK OUT
CRYSTAL OR
CERAMIC
RESONATOR
C1
C2
AD7707
Figure 16. Crystal/Resonator Connection for the AD7707
USING THE AD7707
Clocking and Oscillator Circuit
The AD7707 requires a master clock input, which may be an
external CMOS compatible clock signal applied to the MCLKIN
pin with the MCLKOUT pin left unconnected. Alternatively, a
crystal or ceramic resonator of the correct frequency can be
connected between MCLKIN and MCLKOUT as shown in
Figure 16, in which case the clock circuit will function as an
oscillator, providing the clock source for the part. The input
sampling frequency, the modulator sampling frequency, the
–3dB frequency, output update rate and calibration time are all
directly related to the master clock frequency, f
CLKIN
. Reducing
the master clock frequency by a factor of 2 will halve the above
frequencies and update rate and double the calibration time.
The current drawn from the DV
DD
power supply is also related
to f
CLKIN
. Reducing f
CLKIN
by a factor of 2 will halve the DV
DD
current but will not affect the current drawn from the AV
DD.
Using the part with a crystal or ceramic resonator between the
MCLK IN and MCLK OUT pins generally causes more cur-
rent to be drawn from DV
DD
than when the part is clocked from
a driven clock signal at the MCLK IN pin. This is because the
on-chip oscillator circuit is active in the case of the crystal or
ceramic resonator. Therefore, the lowest possible current on the
AD7707 is achieved with an externally applied clock at the
MCLK IN pin with MCLK OUT unconnected, unloaded and
disabled.
The amount of additional current taken by the oscillator de-
pends on a number of factors—first, the larger the value of
capacitor (C1 and C2) placed on the MCLKIN and MCLKOUT
pins, the larger the current consumption on the AD7707. Care
should be taken not to exceed the capacitor values recom-
mended by the crystal and ceramic resonator manufacturers to
avoid consuming unnecessary current. Typical values for C1
and C2 are recommended by crystal or ceramic resonator
manufacturers, these are in the range of 30 pF to 50 pF and if
the capacitor values on MCLK IN and MCLK OUT are kept in
this range they will not result in any excessive current. Another
factor that influences the current is the effective series resistance
(ESR) of the crystal that appears between the MCLK IN and
MCLK OUT pins of the AD7707. As a general rule, the lower
the ESR value the lower the current taken by the oscillator circuit.
When operating with a clock frequency of 2.4576 MHz, there is
50
μ
A difference in the current between an externally applied
clock and a crystal resonator when operating with a DV
DD
of
+3 V. With DV
DD
= +5 V and f
CLKIN
= 2.4576MHz, the typical
current increases by 250
μ
A for a crystal/resonator supplied
clock versus an externally applied clock. The ESR values for
crystals and resonators at this frequency tend to be low and as a
result there tends to be little difference between different crystal
and resonator types.
When operating with a clock frequency of 1 MHz, the ESR
value for different crystal types varies significantly. As a result,
the current drain varies across crystal types. When using a crys-
tal with an ESR of 700
or when using a ceramic resonator, the
increase in the typical current over an externally-applied clock is
20
μ
A with DV
DD
= +3 V and 200
μ
A with DV
DD
= +5 V. When
using a crystal with an ESR of 3 k
, the increase in the typical
current over an externally applied clock is again 100
μ
A with
DV
DD
= +3 V but 400
μ
A with DV
DD
= +5V.
The on-chip oscillator circuit also has a start-up time associated
with it before it is oscillating at its correct frequency and correct
voltage levels. Typical start-up times with DV
DD
= 5 V are 6 ms
using a 4.9512 MHz crystal, 16 ms with a 2.4576 MHz crystal
and 20 ms with a 1 MHz crystal oscillator. Start-up times are
typically 20% slower when the power supply voltage is reduced
to 3 V. At 3 V supplies, depending on the loading capacitances
on the MCLK pins, a 1 M
feedback resistor may be required
across the crystal or resonator in order to keep the start-up times
around the 20 ms duration.
The AD7707’s master clock appears on the MCLK OUT pin of
the device. The maximum recommended load on this pin is one
CMOS load. When using a crystal or ceramic resonator to gen-
erate the AD7707’s clock, it may be desirable to use this clock
as the clock source for the system. In this case, it is recom-
mended that the MCLK OUT signal is buffered with a CMOS
buffer before being applied to the rest of the circuit.
System Synchronization
The FSYNC bit of the Setup Register allows the user to reset
the modulator and digital filter without affecting any of the
setup conditions on the part. This allows the user to start gath-
ering samples of the analog input from a known point in time,
i.e., when the FSYNC is changed from 1 to 0.
With a 1 in the FSYNC bit of the Setup Register, the digital
filter and analog modulator are held in a known reset state and
the part is not processing any input samples. When a 0 is then
written to the FSYNC bit, the modulator and filter are taken
out of this reset state and the part starts to gather samples again
on the next master clock edge.
The FSYNC input can also be used as a software start convert
command allowing the AD7707 to be operated in a conven-
tional converter fashion. In this mode, writing to the FSYNC bit
starts conversion and the falling edge of
DRDY
indicates when
conversion is complete. The disadvantage of this scheme is that
the settling time of the filter has to be taken into account for
every data register update. This means that the rate at which the
data register is updated is three times slower in this mode.
Since the FSYNC bit resets the digital filter, the full settling
time of 3
×
1/Output Rate has to elapse before there is a new
word loaded to the output register on the part. If the
DRDY
signal is low when FSYNC goes to a 0, the
DRDY
signal will
not be reset high by the FSYNC command. This is because the
AD7707 recognizes that there is a word in the data register
which has not been read. The
DRDY
line will stay low until an
update of the data register takes place, at which time it will go
high for 500
×
t
CLKIN
before returning low again. A read from
the data register resets the
DRDY
signal high and it will not
return low until the settling time of the filter has elapsed (from
the FSYNC command) and there is a valid new word in the
data register. If the
DRDY
line is high when the FSYNC
command is issued, the
DRDY
line will not return low until the
settling time of the filter has elapsed.
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