參數(shù)資料
型號(hào)： AD7707EB
廠商： Analog Devices, Inc.
英文描述： 3 V/5 V 610 V Input Range 1 mW 3-Channel 16-Bit Sigma-Delta ADC(316.51 k)
中文描述： 3伏/ 5伏610 V輸入范圍1毫瓦3通道16位Σ-Δ模數(shù)轉(zhuǎn)換器（316.51十一）
文件頁(yè)數(shù)： 16/40頁(yè)
文件大小： 316K
代理商： AD7707EB
REV. A
AD7707
–16–
Clock Register (RS2, RS1, RS0 = 0, 1, 0); Power-On/Reset Status: 05Hex
The Clock Register is an 8-bit register from which data can either be read or to which data can be written. Table XIII outlines the bit
designations for the Clock Register.
Table XIII. Clock Register
)
0
(
O
R
E
Z
)
0
(
O
R
E
Z
)
0
(
S
I
D
K
L
C
)
0
(
V
I
D
K
L
C
)
1
(
K
L
C
)
0
(
2
S
F
)
0
(
1
S
F
)
1
(
0
S
F
ZERO
Zero. A zero MUST be written to these bits to ensure correct operation of the AD7707. Failure to do so may
result in unspecified operation of the device.
Master Clock Disable Bit. A Logic 1 in this bit disables the master clock from appearing at the MCLK OUT pin.
When disabled, the MCLK OUT pin is forced low. This feature allows the user the flexibility of using the MCLK
OUT as a clock source for other devices in the system or of turning off the MCLK OUT as a power saving feature.
When using an external master clock on the MCLK IN pin, the AD7707 continues to have internal clocks and will
convert normally with the CLKDIS bit active. When using a crystal oscillator or ceramic resonator across the
MCLK IN and MCLK OUT pins, the AD7707 clock is stopped and no conversions take place when the CLKDIS
bit is active.
Clock Divider Bit. With this bit at a Logic 1, the clock frequency appearing at the MCLK IN pin is divided by two
before being used internally by the AD7707. For example, when this bit is set to 1, the user can operate with a
4.9152 MHz crystal between MCLK IN and MCLK OUT and internally the part will operate with the specified
2.4576 MHz. With this bit at a Logic 0, the clock frequency appearing at the MCLK IN pin is the frequency used
internally by the part.
Clock Bit. This bit should be set in accordance with the operating frequency of the AD7707. If the device has a
master clock frequency of 2.4576 MHz (CLKDIV = 0) or 4.9152 MHz (CLKDIV = 1), then this bit should be set
to a “1.” If the device has a master clock frequency of 1 MHz (CLKDIV = 0) or 2 MHz (CLKDIV = 1), this bit
should be set to a “0.” This bit sets up the appropriate scaling currents for a given operating frequency and also
chooses (along with FS2, FS1 and FS0) the output update rate for the device. If this bit is not set correctly for the
master clock frequency of the device, then the AD7707 may not operate to specification.
Filter Selection Bits. Along with the CLK bit, FS2, FS1 and FS0 determine the output update rate, filter
first notch and –3 dB frequency as outlined in Table XIV. The on-chip digital filter provides a sinc
3
(or
Sinx/x
3
) filter response. Placing the first notch at 10 Hz places notches at both 50 and 60 Hz giving better
than 150 dB rejection at these frequencies. In association with the gain selection the filter cutoff also deter-
mines the output noise of the device. Changing the filter notch frequency, as well as the selected gain, im-
pacts resolution. Tables I to IV show the effect of filter notch frequency and gain on the output noise and
effective resolution of the part. The output data rate (or effective conversion time) for the device is equal to
the frequency selected for the first notch of the filter. For example, if the first notch of the filter is selected
at 50 Hz, a new word is available at a 50 Hz output rate or every 20 ms. If the first notch is at 500 Hz, a
new word is available every 2 ms. A calibration should be initiated when any of these bits are changed.
The settling time of the filter to a full-scale step input is worst case 4
×
1/(output data rate). For example,
with the filter first notch at 50 Hz, the settling time of the filter to a full-scale step input is 80 ms max. If
the first notch is at 500 Hz, the settling time is 8 ms max. This settling time can be reduced to 3
×
1/ (out-
put data rate) by synchronizing the step input change to a reset of the digital filter. In other words, if the step
input takes place with the FSYNC bit high, the settling time will be 3
×
1/(output data rate) from when the
FSYNC bit returns low.
The –3 dB frequency is determined by the programmed first notch frequency according to the relationship:
filter –
3
dB frequency =
0.262
×
filter first notch frequency
CLKDIS
CLKDIV
CLK
FS2, FS1, FS0
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