參數(shù)資料
型號(hào)： AD7707BRU
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC
中文描述： 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20
封裝： LOW PROFILE, TSSOP-20
文件頁(yè)數(shù)： 30/40頁(yè)
文件大小： 316K
代理商： AD7707BRU
REV. A
AD7707
–30–
MICROCOMPUTER/MICROPROCESSOR INTERFACING
The AD7707’s flexible serial interface allows for easy interface
to most microcomputers and microprocessors. The flowchart of
Figure 20 outlines the sequence that should be followed when
interfacing a microcontroller or microprocessor to the AD7707.
Figures 21, 22 and 23 show some typical interface circuits.
The serial interface on the AD7707 is capable of operating from
just three wires and is compatible with SPI interface protocols.
The three-wire operation makes the part ideal for isolated sys-
tems where minimizing the number of interface lines minimizes
the number of optoisolators required in the system. The serial
clock input is a Schmitt triggered input to accommodate slow
edges from optocouplers. The rise and fall times of other digital
inputs to the AD7707 should be no longer than 1
μ
s.
Most of the registers on the AD7707 are 8-bit registers, which
facilitates easy interfacing to the 8-bit serial ports of microcon-
trollers. The Data Register on the AD7707 is 16bits, and the
offset and gain registers are 24-bit registers but data transfers to
these registers can consist of multiple 8-bit transfers to the
serial port of the microcontroller. DSP processors and micro-
processors generally transfer 16 bits of data in a serial data
operation. Some of these processors, such as the ADSP-2105,
have the facility to program the amount of cycles in a serial
transfer. This allows the user to tailor the number of bits in any
transfer to match the register length of the required register in
the AD7707.
Even though some of the registers on the AD7707 are only
eight bits in length, communicating with two of these registers
in successive write operations can be handled as a single 16-bit
data transfer if required. For example, if the Setup Register is to
be updated, the processor must first write to the Communica-
tions Register (saying that the next operation is a write to the
Setup Register) and then write eight bits to the Setup Register.
If required, this can all be done in a single 16-bit transfer be-
cause once the eight serial clocks of the write operation to the
Communications Register have been completed, the part imme-
diately sets itself up for a write operation to the Setup Register.
AD7707 to 68HC11 Interface
Figure 21 shows an interface between the AD7707 and the
68HC11 microcontroller. The diagram shows the minimum
(three-wire) interface with
CS
on the AD7707 hard-wired low.
In this scheme, the
DRDY
bit of the Communications Register
is monitored to determine when the Data Register is updated.
An alternative scheme, which increases the number of interface
lines to four, is to monitor the
DRDY
output line from the
AD7707. The monitoring of the
DRDY
line can be done in two
ways. First,
DRDY
can be connected to one of the 68HC11’s
port bits (such as PC0), which is configured as an input. This
port bit is then polled to determine the status of
DRDY
. The
second scheme is to use an interrupt driven system, in which
case the
DRDY
output is connected to the IRQ input of the
68HC11. For interfaces that require control of the
CS
input
on the AD7707, one of the port bits of the 68HC11 (such as
PC1), which is configured as an output, can be used to drive
the
CS
input.
SS
SCK
MISO
MOSI
68HC11
RESET
SCLK
DATA OUT
DATA IN
CS
AD7707
V
DD
V
DD
Figure 21. AD7707 to 68HC11 Interface
The 68HC11 is configured in the master mode with its CPOL
bit set to a logic one and its CPHA bit set to a logic one. When
the 68HC11 is configured like this, its SCLK line idles high
between data transfers. The AD7707 is not capable of full
duplex operation. If the AD7707 is configured for a write op-
eration, no data appears on the DATA OUT lines even when
the SCLK input is active. Similarly, if the AD7707 is config-
ured for a read operation, data presented to the part on the
DATA IN line is ignored even when SCLK is active.
Coding for an interface between the 68HC11 and the
AD7707 is given in Table XV. In this example, the
DRDY
output line of the AD7707 is connected to the PC0 port bit of
the 68HC11 and is polled to determine its status.
P3.0
P3.1
8XC51
RESET
SCLK
DATA OUT
DATA IN
CS
AD7707
V
DD
V
DD
Figure 22. AD7707 to 8XC51 Interface
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