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| 型號(hào)： | AD7707BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 3 V/5 V, +-10 V Input Range, 1 mW 3-Channel 16-Bit, Sigma-Delta ADC |
| 中文描述： | 3-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | LOW PROFILE, TSSOP-20 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 316K |
| 代理商： | AD7707BRU |
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REV. A
AD7707
–20–
ANALOG INPUT
Analog Input Ranges
The AD7707 contains two low level pseudo-differential analog
input channels AIN1 and AIN2. These input pairs provide
programmable-gain, differential input channels that can handle
either unipolar or pseudo bipolar input signals. It should be
noted that the bipolar input signals are referenced to the
LOCOM input. The AD7707 also has a high level analog input
channel AIN 3 which is referenced to HICOM. Figure 11
shows the input structure on the high level input channel.
In normal 5 V operation VBIAS is normally connected to 2.5 V
and HICOM is connected to AGND. This arrangement ensures
that the voltages seen internally are within the common-mode
range of the buffer in buffered mode and within the supply
range in unbuffered mode. This device can be programmed to
operate in either buffered or unbuffered mode via the BUF bit
in the setup register. Note that the signals on AIN3 are with
respect to the HICOM input and not with respect to AGND or
DGND.
The differential voltage seen by the AD7707 when using the
high level input channel is the difference between AIN3(+) and
AIN3(–) on the mux as shown in Figure 11.
AIN
3(+) = (
AIN
3 + 6
×
VBIAS
+
V
(
HICOM
))/8
AIN3
MUX
VBIAS
1R = 5k
V
6R
6R
3R
1R
HICOM
AIN3(–)
AIN3(+)
Figure 11. AIN3 Input Structure
AIN
3(–) =
V
(
HICOM
) + 0.75
×
(
VBIAS
–
V
(
HICOM
))
In unbuffered mode, the common-mode range of the low level
input channels is from AGND – 100 mV to AV
DD
+30 mV.
This means that in unbuffered mode the part can handle both
unipolar and bipolar input ranges for all gains. Absolute volt-
ages of AGND – 100 mV can be accommodated on the analog
inputs without degradation in performance, but leakage current
increases appreciably with increasing temperature. In buffered
mode, the analog inputs can handle much larger source imped-
ances, but the absolute input voltage range is restricted to be-
tween AGND+ 50 mV to AV
DD
– 1.5 V which also places
restrictions on the common-mode range. This means that in
buffered mode there are some restrictions on the allowable
gains for bipolar input ranges. Care must be taken in setting up
the common-mode voltage and input voltage range so that the
above limits are not exceeded, otherwise there will be a degra-
dation in linearity performance.
In unbuffered mode, the analog inputs look directly into the
7pF input sampling capacitor, C
SAMP
. The dc input leakage
current in this unbuffered mode is 1nA maximum. As a result,
the analog inputs see a dynamic load that is switched at the
input sample rate (see Figure 12). This sample rate depends on
master clock frequency and selected gain. C
SAMP
is charged to
AIN(+) and discharged to AIN(–) every input sample cycle.
The effective on-resistance of the switch, R
SW
, is typically 7 k
.
C
SAMP
must be charged through R
SW
and any additional source
impedances every input sample cycle. Therefore, in unbuffered
mode, source impedances mean a longer charge time for C
SAMP
and this may result in gain errors on the part. Table XVI shows
the allowable external resistance/capacitance values, for unbuffered
mode, such that no gain error to the 16-bit level is introduced
on the part. Note that these capacitances are total capacitances
on the analog input. This external capacitance includes 10 pF
from pins and lead frame of the device.
AIN(+)
AIN(–)
SWITCHING FREQUENCY DEPENDS ON
f
CLKIN
AND SELECTED GAIN
R
SW
(7k
V
TYP)
C
(7pF)
FIRST
INTEGRATOR
HIGH INPUT
IMPEDANCE
1G
V
DD
/2
Figure 12. Unbuffered Analog Input Structure
Table XVI. External R, C Combination for No 16-Bit Gain
Error on Low Level Input Channels (Unbuffered Mode Only)
External Capacitance (pF)
50
100
Gain
0
500
1000
5000
1
2
4
8–128
368 k
177.2 k
44.2 k
82.8 k
35.2 k
90.6 k
54.2 k
14.6 k
8.2 k
26.4 k
7.2 k
12.6 k
3.4 k
5.8 k
1.58
2.2 k
1.12 k
4 k
1.94 k
540
880
21.2 k
9.6 k
240
EXTERNAL CAPACITANCE – pF
0
10000
E
V
10
100
1000
0
50
100
150
200
250
300
350
400
GAIN = 1
GAIN = 4
GAIN = 8-128
GAIN = 2
Figure 13. External R, C Combination for No 16-Bit Gain
Error on Low Level Input Channels (Unbuffered Mode Only)
In buffered mode, the analog inputs look into the high imped-
ance inputs stage of the on-chip buffer amplifier. C
SAMP
is
charged via this buffer amplifier such that source impedances do
not affect the charging of C
SAMP
. This buffer amplifier has an
offset leakage current of 1 nA. In buffered mode, large source
impedances result in a small dc offset voltage developed across
the source impedance, but not in a gain error.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7707 | ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75% |
| AD7707EB | 3 V/5 V 610 V Input Range 1 mW 3-Channel 16-Bit Sigma-Delta ADC(316.51 k) |
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| AD7708BRU | 8-/10-Channel, Low Voltage, Low Power, ADCs |
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參數(shù)描述 |
|---|---|
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