參數(shù)資料
型號(hào): AD7707
廠商: Analog Devices, Inc.
英文描述: ECONOLINE: REC2.2-S_DR/H1 - 2.2W DIP Package- 1kVDC Isolation- Regulated Output- UL94V-0 Package Material- Continuous Short Circiut Protection- Internal SMD design- 100% Burned In- Efficiency to 75%
中文描述: 3 V / 5號(hào)第五,1毫瓦3 -10 V輸入范圍通道16位Σ-Δ模數(shù)轉(zhuǎn)換器
文件頁數(shù): 7/40頁
文件大?。?/td> 316K
代理商: AD7707
REV. A
AD7707
–7–
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
SCLK
Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to
access serial data from the AD7707. This serial clock can be a continuous clock with all data
transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with
the information being transmitted to the AD7707 in smaller batches of data.
Master Clock signal for the device. This can be provided in the form of a crystal/resonator or
external clock. A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins.
Alternatively, the MCLK IN pin can be driven with a CMOS-compatible clock and MCLK
OUT left unconnected. The part can be operated with clock frequencies in the range 500kHz to
5 MHz.
When the master clock for the device is a crystal/resonator, the crystal/resonator is connected
between MCLK IN and MCLKOUT. If an external clock is applied to MCLK IN, MCLK
OUT provides an inverted clock signal. This clock can be used to provide a clock source for
external circuitry and is capable of driving one CMOS load. If the user does not require it, this
MCLK OUT can be turned off via the CLK DIS bit of the Clock Register. This ensures that the
part is not wasting unnecessary power driving capacitive loads on MCLK OUT.
Chip Select. Active low Logic Input used to select the AD7707. With this input hard-wired low,
the AD7707 can operate in its three-wire interface mode with SCLK, DIN and DOUT used to
interface to the device.
CS
can be used to select the device in systems with more than one device
on the serial bus or as a frame synchronization signal in communicating with the AD7707.
Logic Input. Active low input that resets the control logic, interface logic, calibration coeffi-
cients, digital filter and analog modulator of the part to power-on status.
Analog Supply Voltage, +2.7 V to +5.25 V operation.
Low Level Analog Input Channel 1. This is used as a pseudo-differential input with respect to
LOCOM.
COMMON Input for low level input channels. Analog inputs on AIN1 and AIN2 must be refer-
enced to this input.
Low Level Analog Input Channel 2. This is used as a pseudo-differential input with respect to
LOCOM.
Single-Ended High Level Analog Input Channel with respect to HICOM.
COMMON Input for high level input channel. Analog input on AIN3 must be referenced to
this input.
VBIAS is used to level shift the high level input channel signal. This signal is used to ensure that
the AIN(+) and AIN(–) signals seen by the internal modulator are within its common-mode
range. VBIAS is normally connected to 2.5 V when AV
DD
= 5 V and 1.225 V when AV
DD
= 3 V.
Reference Input. Positive input of the differential reference input to the AD7707. The reference
input is differential with the provision that REF IN(+) must be greater than REF IN(–).
REFIN(+) can lie anywhere between AV
DD
and AGND.
2
MCLK IN
3
MCLK OUT
4
CS
5
RESET
6
7
AV
DD
AIN1
8
LOCOM
9
AIN2
10
11
AIN3
HICOM
12
VBIAS
13
REF IN(+)
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD7707
AIN3
AIN2
LOCOM
MCLK IN
MCLK OUT
CS
AIN1
AV
DD
RESET
HICOM
VBIAS
REF IN(+)
DV
DD
DIN
DOUT
REF IN(–)
AGND
DRDY
SCLK
DGND
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