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參數(shù)資料
| 型號： | AD7683BCPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 100KSPS 8LFCSP |
| 標準包裝： | 5,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 6mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-WDFN 裸露焊盤，CSP |
| 供應商設備封裝： | 8-LFCSP-WD |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
AD7683
Rev. A | Page 12 of 16
APPLICATIONS INFORMATION
SW+
MSB
16,384C
+IN
LSB
COMP
CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
–IN
4C
2C
C
32,768C
SW–
MSB
16,384C
LSB
4C
2C
C
32,768C
04301-020
Figure 20. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7683 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture.
The AD7683 is capable of converting 100,000 samples per
second (100 kSPS) and powers down between conversions.
When operating at 10 kSPS, for example, it consumes typi-
cally 150 μW with a 2.7 V supply, ideal for battery-powered
applications.
The AD7683 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7683 is specified from 2.7 V to 5.5 V. It is housed in an
8-lead MSOP or a tiny, 8-lead QFN (LFCSP) package.
The AD7683 is an improved second source to the ADS8320 and
ADS8325. For even better performance, consider the AD7685.
CONVERTER OPERATION
The AD7683 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors that connect
to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the +IN and IN inputs. When the
acquisition phase is complete and the CS input goes low, a con-
version phase is initiated. When the conversion phase begins,
SW+ and SW are opened first. The two capacitor arrays are
then disconnected from the inputs and connected to the GND
input. Therefore, the differential voltage between the inputs,
+IN and IN, captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (VREF/2, VREF/4...VREF/65,536).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the acquisition
phase and the control logic generates the ADC output code.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7683 is shown in Figure 21
and Table 9.
000...000
000...001
000...010
111...101
111...110
111...111
ADC
CO
DE
(
S
T
RA
IG
H
T
BI
N
A
R
Y)
ANALOG INPUT
+FS – 1.5 LSB
+FS – 1 LSB
–FS + 1 LSB
–FS
–FS + 0.5 LSB
04
30
1-
0
21
Figure 21. ADC Ideal Transfer Function
Table 9. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 5 V
Digital Output Code
Hexadecimal
FSR – 1 LSB
4.999924 V
Midscale + 1 LSB
2.500076 V
8001
Midscale
2.5 V
8000
Midscale – 1 LSB
2.499924 V
7FFF
–FSR + 1 LSB
76.3 μV
0001
–FSR
0 V
1 This is also the code for an overranged analog input (V+IN – V–IN above
VREF – VGND).
2 This is also the code for an underranged analog input (V+IN – V–IN below VGND).
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