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參數(shù)資料
| 型號： | AD7677ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 1MSPS DIFF 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 130mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 778 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7677CBZ-ND - BOARD EVALUATION FOR AD7677 |
REV. A
AD7677
–17–
SERIAL INTERFACE
The AD7677 is configured to use the serial interface when the
SER/PAR is held high. The AD7677 outputs 16 bits of data,
MSB first, on the SDOUT Pin. This data is synchronized with
the 16 clock pulses provided on the SCLK Pin.
MASTER SERIAL INTERFACE
Internal Clock
The AD7677 is configured to generate and provide the serial
data clock SCLK when the EXT/
INT Pin is held low. The AD7677
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. The output data is valid on both the
rising and falling edge of the data clock. Depending on RDC/
SDIN input, the data can be read after each conversion, or during
the following conversion.
Figure 17 and Figure 18 show the detailed timing diagrams of
these two modes.
Usually, because the AD7677 is used with a fast throughput, the
mode master, read during conversion, is the most recommended
serial mode when it can be used.
In read-after-conversion mode, unlike in other modes, it should
be noted that the signal BUSY returns low after the 16 data bits
are pulsed out and not at the end of the conversion phase, which
results in a longer BUSY width.
In read-during-conversion mode, the serial clock and data toggle at
appropriate instances minimizes potential feedthrough between
digital activity and the critical conversion decisions.
To accommodate slow digital hosts, the serial clock can be
slowed down by using DIVSCLK.
SLAVE SERIAL INTERFACE
External Clock
The AD7677 is configured to accept an externally supplied serial
data clock on the SCLK pin when the EXT/
INT pin is held
high. In this mode, several methods can be used to read the
data. The external serial clock is gated by
CS and the data are
output when both
CS and RD are low. Thus, depending on CS,
the data can be read after each conversion or during the follow-
ing conversion. The external clock can be either a continuous
or discontinuous clock. A discontinuous clock can be either
CS
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
BUSY
SDIN
INVSCLK = 0
X15
X14
X
12
3
14
15
16
17
18
EXT/
INT = 1
RD = 0
t35
t36 t37
t31
t32
t34
t16
t33
Figure 19. Slave Serial Data Timing for Reading (Read After Convert)
CNVST
SDOUT
SCLK
D1
D0
X
D15
D14
D13
12
3
14
15
16
BUSY
INVSCLK = 0
CS
EXT/
INT = 1
RD = 0
t35
t36
t37
t31
t32
t16
t3
Figure 20. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7677ASTZ | 制造商:Analog Devices 功能描述:IC 16-BIT ADC |
| AD7677ASTZRL | 功能描述:IC ADC 16BIT 1MSPS DIFF 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7678 | 制造商:AD 制造商全稱:Analog Devices 功能描述:18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC |
| AD7678ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 18-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:18-BIT,100KSPSSARADC - Bulk 制造商:Analog Devices 功能描述:18BIT SAR ADC SMD 7678 LFSCP-48 |
| AD7678ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 100ksps 18-bit Parallel/Serial 48-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 100KSPS 18BIT PARALLEL/SERL 48LFCSP EP - Tape and Reel 制造商:Rochester Electronics LLC 功能描述:18-BIT,100KSPSSARADC - Bulk |
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