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參數(shù)資料
| 型號： | AD7671 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| 中文描述： | 16位1 MSPS的特區(qū)單極型ADC檔 |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 336K |
| 代理商： | AD7671 |
REV. PrA
PRELIMINARY TECHNICAL DATA
–6–
AD7667
PIN FUNCT ION DESCRIPT IONS
Pin No.
Mnemonic
T ype
Description
1
2
3, 40–42,
44
4
AGND
AVDD
NC
P
P
Analog Power Ground Pin
Input Analog Power Pins. Nominally 5 V.
No Connect
BY T ESWAP
DI
Parallel Mode Selection (8/16 bit). When LOW, the LSB is output on D[7:0] and the
MSB is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB
is output on D[7:0].
Straight Binary/Binary T wo’s Complement. When OB/
2C
is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a two’s complement output
from its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,
the maximum throughput is achievable, and a minimum conversion rate must be applied
in order to guarantee full specified accuracy. When LOW, full accuracy is maintained
independent of the minimum conversion rate.
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the
serial interface mode is selected and some bits of the DAT A bus are used as a serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
PAR
is HIGH, these
outputs are in high impedance.
When SER/
PAR
is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port
Data Output Bus. When SER/
PAR
is HIGH
,
EX T /
INT
is LOW, and RDC/SDIN is
LOW, which is serial master read after convert, these inputs, part of the serial port, are
used to slow down if desired the internal serial clock which clocks the data output. In
other serial moes, these pins are not used
When SER/
PAR
is LOW, this output is used as Bit 4 of the Parallel Port Data Output
Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as a digital select input
for choosing the internal or an external data clock. With EX T /
INT
tied LOW, the internal
clock
is selected on SCLK output. With EX T /
INT
set to a logic HIGH, output data is syn
chronized
to an external clock signal connected to the SCLK input.
When SER/
PAR
is LOW, this output is used as Bit 5 of the Parallel Port Data Output
Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to select the active
5
OB/
2C
DI
6
WARP
DI
7
IMPUL SE
DI
8
SER/
PAR
DI
9,10
DAT A[0:1]
DI
11,12
DAT A[2:3]or
DI/O
DIVSCLK [0:1]
13
DAT A[4]
DI/O
or EX T /
INT
14
DAT A[5]
DI/O
or INVSYNC
PIN CONFIGURAT ION
48-L ead L QFP
(ST -48)
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
D
1
2
3
4
5
6
7
8
9
10
11
12
48 47 46 45 44
39 38 37
43 42 41 40
PIN 1
TOP VIEW
(Not to Scale)
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12
AGND
AVDD
NC
BYTESWAP
OB/2C
WARP
IMPULSE
SER/PAR
NC = NO CONNECT
D0
D1
D2/SCLK0
D3/SCLK1
AD7667
D
D
D
O
O
D
D
D
D
D
D
P
P
R
T
N
I
N
N
N
I
R
R
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