參數(shù)資料
型號: AD7671
廠商: Analog Devices, Inc.
英文描述: 16-Bit 1 MSPS SAR Unipolar ADC with Ref
中文描述: 16位1 MSPS的特區(qū)單極型ADC檔
文件頁數(shù): 18/23頁
文件大?。?/td> 336K
代理商: AD7671
REV. PrA
PRELIMINARY TECHNICAL DATA
–18–
AD7667
t
1
t
3
t
4
t
11
CNVST
BUSY
DATA
BUS
CS = RD = 0
t
10
PREVIOUS CONVERSION DATA
NEW DATA
Figure 13. Master Parallel Data Timing for Reading
(Continuous Read)
PARAL L E L INT E RF AC E
T he AD7667 is configured to use the parallel interface when
the SER/
PAR
is held low. T he data can be read either after
each conversion, which is during the next acquisition phase,
or during the following conversion as shown, respectively, in
Figure 14 and Figure 15. When the data is read during the
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. T hat avoids
any potential feedthrough between voltage transients on the
digital interface and the most critical analog conversion cir-
cuitry.
CCURRENT
BUSY
BUS
CS
RD
t
12
t
13
Figure 14. Slave Parallel Data Timing for Reading
(Read After Convert)
T he BYT ESWAP pin allows a glueless interface to a 8 bits
bus. As shown in Figure T BD, the LSB byte is output on
D[7:0] and the MSB is output on D[15:8] when
BYT ESWAP is low. When BYT ESWAP is high, the LSB and
MSB bytes are swapped and the LSB is output on D[15:8]
and the MSB is output on D[7:0]. By connecting
BYT ESWAP to an address line, the 16 bits data can be read
in 2 bytes on either D[15:8] or D[7:0].
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
CS
BUSY
SDIN
EXT/INT = 1
INVSCLK = 0
t
35
t
36
t
37
t
31
t
32
t
16
t
33
t
34
X15
X14
X
1
2
3
14
15
16
17
18
RD
= 0
Figure 18. Slave Serial Data Timing for Reading (Read After Convert)
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