參數(shù)資料
型號(hào)： AD7663ASTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 21/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT CMOS 48-LQFP T/R
產(chǎn)品培訓(xùn)模塊： Power Line Monitoring
標(biāo)準(zhǔn)包裝： 2,000
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 250k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 41mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 4 個(gè)單端，單極；4 個(gè)單端，雙極
配用： EVAL-AD7663CBZ-ND - BOARD EVALUATION FOR AD7663
REV. B
AD7663
–6–
PIN FUNCTION DESCRIPTION
Pin
No.
Mnemonic
Type
Description
1
AGND
P
Analog Power Ground Pin.
2
AVDD
P
Input Analog Power Pin. Nominally 5 V.
3, 6, 7,
NC
No Connect.
44–48
4
BYTESWAP
DI
Parallel Mode Selection (8/16 Bit). When LOW, the LSB is output on D[7:0] and the MSB is output
on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is output on D[7:0].
5OB/
2C
DI
Straight Binary/Binary Twos Complement. When OB/
2C is HIGH, the digital output is straight
binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal
shift register.
8
SER/
PAR
DI
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the
Serial Interface Mode is selected and some bits of the Data bus are used as a Serial Port.
9, 10
D[0:1]
DO
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/
PAR is HIGH, these outputs
are in high impedance.
11, 12
D[2:3] or
DI/O
When SER/
PAR is LOW, these outputs are used as Bit 2 and Bit 3 of the Parallel Port Data
Output Bus.
DIVSCLK[0:1]
When SER/
PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the Serial
Master Read after Convert Mode. These inputs, part of the Serial Port, are used to slow down,
if desired, the internal serial clock that clocks the data output. In the other serial modes, these
pins are high impedance outputs.
13
D[4]
DI/O
When SER/
PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.
or EXT/
INT
When SER/
PAR is HIGH, this input, part of the Serial Port, is used as a digital select input for
choosing the internal or an external data clock, called respectively, Master and Slave Modes.
With EXT/
INT tied LOW, the internal clock is selected on SCLK output. With EXT/INT
set to a logic HIGH, output data is synchronized to an external clock signal connected to the
SCLK input, and external clock is gated by
CS.
14
D[5]
DI/O
When SER/
PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.
or INVSYNC
When SER/
PAR is HIGH, this input, part of the Serial Port, is used to select the active state of
the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
15
D[6]
DI/O
When SER/
PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
or INVSCLK
When SER/
PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK signal.
It is active in both master and slave mode.
16
D[7]
DI/O
When SER/
PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN
When SER/
PAR is HIGH, this input, part of the Serial Port, is used as either an external data
input or a read mode selection input, depending on the state of EXT/
INT.
When EXT/
INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion
results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is
output on DATA with a delay of 16 SCLK periods after the initiation of the read sequence.
When EXT/
INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is
HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW,
the data can be output on SDOUT only when the conversion is complete.
17
OGND
P
Input/Output Interface Digital Power Ground.
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
19
DVDD
P
Digital Power. Nominally at 5 V.
20
DGND
P
Digital Power Ground.
相關(guān)PDF資料
PDF描述
ADN4692EBRZ-RL7 IC TXRX MLVDS 100MBPS 8SOIC
VE-23F-MX-F4 CONVERTER MOD DC/DC 72V 75W
VE-23F-MX-F3 CONVERTER MOD DC/DC 72V 75W
VE-263-CU-F4 CONVERTER MOD DC/DC 24V 200W
AD7824KR-REEL IC ADC 8BIT LC2MOS 4CH HS 24SOIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7663CB1 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 250 kSPS CMOS ADC
AD7664 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit, 570 kSPS CMOS ADC
AD7664ACP 制造商:Analog Devices 功能描述:ADC Single SAR 570ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Analog Devices 功能描述:ADC SGL SAR 570KSPS 16BIT PARALLEL/SERL 48LFCSP EP - Trays 制造商:Rochester Electronics LLC 功能描述:16-BIT, 500KSPS CMOS ADC - Bulk
AD7664ACPRL 制造商:Analog Devices 功能描述:ADC Single SAR 570ksps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R
AD7664ACPZ 功能描述:IC ADC 16BIT UNIPOLAR 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*