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參數(shù)資料
| 型號： | AD7660AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS CMOS ADC |
| 中文描述： | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, PQFP48 |
| 封裝： | MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 218K |
| 代理商： | AD7660AST |
REV. 0
AD7660
–17–
External Discontinuous Clock Data Read after Conversion
This mode is the most recommended of the serial slave modes.
Figure 18 shows the detailed timing diagrams of this method.
After a conversion is complete, indicated by BUSY returning
low, the result of this conversion can be read while both
CS
and
RD
are low. The data is shifted out, MSB first, with 16 clock
pulses and is valid on both rising and falling edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there is no voltage transients on
the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed up
to 40 MHz which accommodates both slow digital host interface
and the fastest serial reading.
Finally, in this mode only, the AD7660 provides a “daisy chain”
feature using the RDC/SDIN input pin for cascading multiple
converters together. This feature is useful for reducing compo-
nent count and wiring connections when it is desired as it is, for
instance, in isolated multiconverters applications.
An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a common
CNVST
signal. It should be noted that the RDC/SDIN input is
latched on the opposite edge of SCLK of the one used to shift
out the data on SDOUT. Hence, the MSB of the “upstream”
converter just follows the LSB of the “downstream” converter
on the next SCLK cycle. Up to twenty AD7660s running at
100 kSPS can be “daisy chained” using this method.
RDC/SDIN
BUSY
BUSY
DATA
OUT
AD7660
#1
(DOWNSTREAM)
BUSY
OUT
CNVST
CS
SCLK
AD7660
#2
(UPSTREAM)
RDC/SDIN
SDOUT
SCLK IN
CS IN
CNVST IN
CNVST
CS
SCLK
SDOUT
Figure 19. Two AD7660s in a “Daisy Chain” Configuration
External Clock Data Read During Conversion
Figure 20 shows the detailed timing diagrams of this method.
During a conversion, while both
CS
and
RD
are low, the result
of the previous conversion can be read. The data is shifted out,
MSB first, with 16 clock pulses, and is valid on both rising and
falling edges of the clock. The 16 bits have to be read before the
current conversion is complete. If that is not done, RDERROR is
pulsed high and can be used to interrupt the host interface to
prevent incomplete data reading. There is no “daisy chain”
feature in this mode, and RDC/SDIN input should always be
tied either high or low.
To reduce performance degradation due to digital activity, a fast
discontinuous clock of 18 MHz at least is recommended to ensure
that all the bits are read during the first half of the conversion
phase. For this reason, this mode is more difficult to use.
SCLK
SDOUT
D15
D14
D1
D0
D13
X15
X14
X13
X1
X0
Y15
Y14
CS
,
RD
BUSY
SDIN
EXT/I
NT
= 1
INVSCLK = 0
t
35
t
36
t
37
t
31
t
32
t
16
t
33
t
34
X15
X14
X
1
2
3
14
15
16
17
18
Figure 18. Slave Serial Data Timing for Reading (Read after Convert)
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