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| 型號(hào)： | AD7655ACPZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 4CHAN 48LFCSP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 135mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP-VQ（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極 |
| 配用： | EVAL-AD7655CBZ-ND - BOARD EVALUATION FOR AD7655 |
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AD7655
Rev. B | Page 18 of 28
CONVERSION CONTROL
Figure 21 shows a detailed timing diagram of the conversion
process. The AD7655 is controlled by the signal CNVST,
which initiates conversion. Once initiated, it cannot be
restarted or aborted, even by the power-down input, PD,
until the conversion is complete. The CNVST signal operates
independently of the CS and RD signals.
BUSY
ACQUIRE
t2
t1
t3
t4
t5
t6
t7
t8
CONVERT A
ACQUIRE
CONVERT
CONVERT B
t12
A0
t14
t15
t13
t11
t10
EOC
CNVST
03536-021
MODE
Figure 21. Basic Conversion Timing
Although CNVST is a digital signal, it should be designed with
special care with fast, clean edges and levels, and with minimum
overshoot and undershoot or ringing.
For applications where the SNR is critical, the CNVST signal
should have very low jitter. One solution is to use a dedicated
oscillator for CNVST generation or, at least, to clock it with a
high frequency low jitter clock, as shown in Figure 17.
In impulse mode, conversions can be automatically initiated. If
CNVST is held low when BUSY is low, the AD7655 controls the
acquisition phase and automatically initiates a new conversion.
By keeping CNVST low, the AD7655 keeps the conversion
process running by itself. Note that the analog input has to be
settled when BUSY goes low. Also, at power-up, CNVST should
be brought low once to initiate the conversion process. In this
mode, the AD7655 can sometimes run slightly faster than the
guaranteed limits of 888 kSPS in impulse mode. This feature
does not exist in normal mode.
DIGITAL INTERFACE
The AD7655 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or parallel interface.
The serial interface is multiplexed on the parallel data bus. The
AD7655 digital interface accommodates either 3 V or 5 V logic
when the OVDD supply pin of the AD7655 is connected to the
host system interface digital supply.
The two signals, CS and RD, control the interface. When at
least one of these signals is high, the interface outputs are in
high impedance. Usually CS allows the selection of each
AD7655 in multicircuit applications and is held low in a single
AD7655 design. RD is generally used to enable the conversion
result on the data bus. In parallel mode, signal A/B allows the
choice of reading either the output of Channel A or Channel B,
whereas in serial mode, signal A/B controls which channel is
output first.
Figure 22 details the timing when using the RESET input. Note
the current conversion, if any, is aborted and the data bus is
high impedance while RESET is high.
t9
RESET
DATA
BUS
BUSY
t8
CNVST
03536-022
Figure 22. Reset Timing
PARALLEL INTERFACE
The AD7655 is configured to use the parallel interface when
SER/PAR is held low.
Master Parallel Interface
Data can be read continuously by tying CS and RD low, thus
requiring minimal microprocessor connections. However, in
this mode the data bus is always driven and cannot be used in
shared bus applications (unless the device is held in RESET).
Figure 23 details the timing for this mode.
t1
t3
t4
t17
BUSY
DATA
BUS
t16
NEW A
OR B
PREVIOUS CHANNEL A
OR B
PREVIOUS CHANNEL B
OR NEW A
t10
CS = RD = 0
EOC
CNVST
03536-023
Figure 23. Master Parallel Data Timing for Reading (Continuous Read)
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| AD7655AST | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7655 LQFP48 |
| AD7655ASTRL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP T/R |
| AD7655ASTZ | 功能描述:IC ADC 16BIT 1MSPS QUAD 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
| AD7655ASTZ | 制造商:Analog Devices 功能描述:CONVERTER A/D ((NW)) |
| AD7655ASTZRL | 功能描述:IC ADC 16BIT 4CHAN 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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