參數(shù)資料
型號(hào)： AD7655ACP
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： Low Cost 4-Channel 1 MSPS 16-Bit ADC
中文描述： 4-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, QCC48
封裝： 7 X 7 MM, MO-220-VKKD-2, LFCSP-48
文件頁(yè)數(shù)： 7/20頁(yè)
文件大?。?/td> 684K
代理商： AD7655ACP
REV. 0
AD7655
–7–
PIN FUNCTION DESCRIPTIONS
Pin
Number
Mnemonic
Type
Description
15
D[6]
or INVSCLK
DI/O
When SER/
PAR
is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used to invert the SCLK signal.
It is active in both master and slave mode.
When SER/
PAR
is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this input, part of the serial port, is used as either an external data
input or a read mode selection input depending on the state of EXT/
INT
. When EXT/
INT
is
HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from
two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT
with a delay of 32 SCLK periods after the initiation of the read sequence.
When EXT/
INT
is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is
HIGH, the previous data is output on SDOUT during conversion. When RDC/SDIN is LOW,
the data can be output on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power Ground
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
When SER/
PAR
is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7655
provides the two conversion results, MSB first, from its internal shift register. The order of channel
outputs is controlled by A/
B
. In serial mode, when EXT/
INT
is LOW, SDOUT is valid on both
edges of SCLK.
In serial mode, when EXT/
INT
is HIGH:
If INVSCLK is LOW, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
When SER/
PAR
is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this pin, part of the serial port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/
INT
pin. The active edge where the data
SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/
PAR
is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/
INT
= Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames
SDOUT. After the first channel is output, SYNC is pulsed LOW.
When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains
LOW while SDOUT output is valid. After the first channel is output, SYNC is pulsed HIGH.
When SER/
PAR
is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
When SER/
PAR
is HIGH and EXT/
INT
is HIGH, this output, part of the serial port, is used
as a incomplete read error flag. In slave mode, when a data read is started and not complete when
the following conversion is complete, the current data is lost and RDERROR is pulsed high.
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. When SER/
PAR
is HIGH, these outputs
are in high impedance.
Busy Output. Transitions HIGH when a conversion is started, and remains HIGH until the
two conversions are complete and the data are latched into the on-chip shift register. The falling
edge of BUSY could be used as a data ready clock signal.
End of Convert Output. Going low at each channel conversion.
Read Data. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is enabled.
Chip Select. When
CS
and
RD
are both LOW, the interface parallel or serial output bus is
enabled.
CS
is also used to gate the external serial clock.
Reset Input. When set to a logic HIGH, reset the AD7655. Current conversion if any is aborted.
If not used, this pin could be tied to DGND.
16
D[7]
or RDC/SDIN
DI/O
17
18
OGND
OVDD
P
P
19, 36
21
DVDD
D[8]
or SDOUT
P
DO
22
D[9]
or SCLK
DI/O
23
D[10]
or SYNC
DO
24
D[11]
or RDERROR
DO
25
–
28
D[12:15]
DO
29
BUSY
DO
30
31
32
EOC
RD
CS
DO
DI
DI
33
RESET
DI
相關(guān)PDF資料
PDF描述
AD7655ACPRL Low Cost 4-Channel 1 MSPS 16-Bit ADC
AD7655AST Low Cost 4-Channel 1 MSPS 16-Bit ADC
AD7655ASTRL Low Cost 4-Channel 1 MSPS 16-Bit ADC
AD7660 Circular Connector; No. of Contacts:4; Series:D38999; Body Material:Metal; Connecting Termination:Crimp; Connector Shell Size:13; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:13-4
AD7660AST 16-Bit, 100 kSPS CMOS ADC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7655ACPRL 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R
AD7655ACPZ 功能描述:IC ADC 16BIT 4CH 48-LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤(pán)（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁(yè)面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6
AD7655ACPZRL 功能描述:IC ADC 16BIT 4CHAN 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極
AD7655AST 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7655 LQFP48
AD7655ASTRL 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LQFP T/R
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