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參數(shù)資料
| 型號： | AD7651ASTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 100KSPS 48-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 2 個偽差分，單極 |
| 產(chǎn)品目錄頁面： | 778 (CN2011-ZH PDF) |
| 配用： | EVAL-AD7651CBZ-ND - BOARD EVALUATION FOR AD7651 |
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AD7651
CURRENT
CONVERSION
BUSY
DATA
BUS
t12
t13
02964-0-013
RD
CS
DIGITAL INTERFACE
The AD7651 has a versatile digital interface; it can be interfaced
with the host system by using either a serial or a parallel
interface. The serial interface is multiplexed on the parallel data
bus. The AD7651 digital interface also accommodates both 3 V
and 5 V logic by simply connecting the OVDD supply pin of the
AD7651 to the host system interface digital supply. Finally, by
using the OB/2C input pin, both twos complement or straight
binary coding can be used.
The two signals, CS and RD, control the interface. CS and RD
have a similar effect because they are OR’d together internally.
When at least one of these signals is HIGH, the interface
outputs are in high impedance. Usually CS allows the selection
of each AD7651 in multicircuit applications and is held low in a
single AD7651 design. RD is generally used to enable the
conversion result on the data bus.
PARALLEL INTERFACE
The AD7651 is configured to use the parallel interface when
SER/PARis held LOW. The data can be read either after each
conversion, which is during the next acquisition phase, or
during the following conversion, as shown in F
, respectively. When the data is read during the
conversion, however, it is recommended that it is read only
during the first half of the conversion phase. This avoids any
potential feedthrough between voltage transients on the digital
interface and the most critical analog conversion circuitry.
Figure 29. Slave Parallel Data Timing for Reading (Read after Convert)
Figure 30. Slave Parallel Data Timing for Reading (Read during Convert)
PREVIOUS
CONVERSION
t1
t3
t12
t13
t4
BUSY
DATA
BUS
02964-0-014
CNVST,
RD
CS = 0
The BYTESWAP pin allows a glueless interface to an 8-bit bus.
As shown in
, the LSB byte is output on D[7:0] and the
MSB is output on D[15:8] when BYTESWAP is LOW. When
BYTESWAP is HIGH, the LSB and MSB bytes are swapped and
the LSB is output on D[15:8] and the MSB is output on D[7:0].
By connecting BYTESWAP to an address line, the 16-bit data
can be read in two bytes on either D[15:8] or D[7:0].
Figure 31. 8-Bit Parallel Interface
CS
RD
BYTESWAP
PINS D[15:8]
PINS D[7:0]
HI-Z
HIGH BYTE
LOW BYTE
HIGH BYTE
HI-Z
t12
t13
02964-0-025
SERIAL INTERFACE
The AD7651 is configured to use the serial interface when
SER/PAR is held HIGH. The AD7651 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edges of the data clock.
Rev. 0 | Page 20 of 28
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7651ASTZ | 制造商:Analog Devices 功能描述:16BIT SAR ADC REF 7651 LQFP48 |
| AD7651ASTZRL | 功能描述:IC ADC 16BIT UNIPOLAR 48LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD7652 | 制造商:AD 制造商全稱:Analog Devices 功能描述:16-Bit 1 MSPS SAR Unipolar ADC with Ref |
| AD7652ACP | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:16-BIT 500KSPS SAR UNIPOLAR ADC W/ REF - Bulk 制造商:Analog Devices 功能描述:16BIT SAR ADC REF 7652 LFSCP-48 |
| AD7652ACPRL | 制造商:Analog Devices 功能描述:ADC Single SAR 500ksps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R |
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