- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10527 > AD7643BSTZ (Analog Devices Inc)IC ADC 18BIT DIFFER W/REF 48LQFP PDF資料下載
參數(shù)資料
| 型號： | AD7643BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT DIFFER W/REF 48LQFP |
| 標準包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | EVAL-AD7643CBZ-ND - BOARD EVALUATION FOR AD7643 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁
AD7643
Rev. 0 | Page 9 of 28
Pin
No.
Mnemonic
Type1
Description
14
D7
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus.
or INVSYNC
When MODE[1:0] = 3 (serial mode), invert sync select. In serial master mode (EXT/INT = low), this
input is used to select the active state of the SYNC signal.
When INVSYNC = low, SYNC is active high.
When INVSYNC = high, SYNC is active low.
15
D8
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus.
or INVSCLK
When MODE[1:0] = 3 (serial mode), invert SCLK select. In all serial modes, this input is used to
invert the SCLK signal.
16
D9
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus.
or RDC
When MODE[1:0] = 3 (serial mode), read during convert. When using serial master mode
(EXT/INT = low), RDC is used to select the read mode.
When RDC = high, the previous conversion result is output on SDOUT during conversion and
the period of SCLK changes (see the Master Serial Interface section).
When RDC = low (read after convert), the current result can be output on SDOUT only when
the conversion is complete.
or SDIN
When MODE[1:0] = 3 (serial mode), serial data in. When using serial slave mode (EXT/INT = high),
SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs
onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK
periods after the initiation of the read sequence.
17
OGND
P
Input/Output Interface Digital Power Ground.
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the
host interface (2.5 V or 3 V).
19
DVDD
P
Digital Power. Nominally at 2.5 V.
20
DGND
P
Digital Power Ground.
21
D10
DO
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus.
or SDOUT
When MODE[1:0] = 3 (serial mode), serial data output. In serial mode, this pin is used as the serial
data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7643
provides the conversion result, MSB first, from its internal shift register. The data format is
determined by the logic level of OB/2C.
In master mode, EXT/INT = low. SDOUT is valid on both edges of SCLK.
In slave mode, EXT/INT = high:
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.
22
D11
DI/O
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus.
or SCLK
When MODE[1:0] = 3 (serial mode), serial clock. In all serial modes, this pin is used as the serial
data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge
where the data SDOUT is updated depends on the logic state of the INVSCLK pin.
23
D12
DO
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus.
or SYNC
When MODE[1:0] = 3 (serial mode), frame synchronization. In serial master mode (EXT/INT= low),
this output is used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high
while SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low
while SDOUT output is valid.
24
D13
DO
When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus.
or RDERROR
When MODE[1:0] = 3 (serial mode), read error. In serial slave mode (EXT/INT = high), this output
is used as an incomplete read error flag. If a data read is started and not completed when the
current conversion is complete, the current data is lost and RDERROR is pulsed high.
25 to
28
D[14:17]
DO
Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs, regardless of
the interface mode.
29
BUSY
DO
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal.
30
DGND
P
Digital Power Ground.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD5590BBCZ | IC ADC I/O PORT-16 AMP 80-CSPBGA |
| ICL3243EIVZ | IC 3DRVR/5RCVR RS232 3V 28-TSSOP |
| AD7985BCPZ | IC ADC 16B 2.5MSPS PULSR 20LFCSP |
| ICL3245ECAZ | IC 3DRVR/5RCVR RS232 3V 28-SSOP |
| VI-J4L-MW-F3 | CONVERTER MOD DC/DC 28V 100W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7643BSTZRL | 功能描述:IC ADC 18BIT DIFFER W/REF 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應(yīng)商設(shè)備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7645AQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645BQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645CQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
| AD7645GCQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit Buffered Miltiplying CMOS D/A Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。