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參數(shù)資料
型號： AD7634BCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 24/32頁
文件大小： 0K
描述： IC ADC 18BIT DIFF BIPO 48-LFCSP
標準包裝： 2,500
系列： PulSAR®
位數(shù)： 18
采樣率（每秒）： 670k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 225mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應商設備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個差分，單極；1 個差分，雙極
AD7634
Data Sheet
Rev. B | Page 30 of 32
SCIN
SCCLK
WARP
START
TEN
123
67
BUSY
HW/SW = 0
INVSCLK = 0
CNVST
SCCS
t8
t36
t35
t37
4
PD
5
BIPOLAR
IMPULSE
OB/2C
X
89
MODE[1:0] = 3
BIPOLAR = 0 OR 1
TEN = 0 OR 1
IMPULSE = 0 OR 1
WARP = 0 OR 1
PD = 0
t33
t34
t31
X
t31
06
40
6-
0
44
Figure 47. Serial Configuration Port Timing
MICROPROCESSOR INTERFACING
The AD7634 is ideally suited for traditional dc measurement
applications supporting a microprocessor, and ac signal proc-
essing applications interfacing to a digital signal processor. The
AD7634 is designed to interface with a parallel 8-bit or 18-bit wide
interface, or with a general-purpose serial port or I/O ports on a
microcontroller. A variety of external buffers can be used with
the AD7634 to prevent digital noise from coupling into the ADC.
SPI Interface
The AD7634 is compatible with SPI and QSPI digital hosts
and DSPs, such as Blackfin ADSP-BF53x and ADSP-218x/
ADSP-219x. Figure 48 shows an interface diagram between
the AD7634 and the SPI-equipped ADSP-219x. To accom-
modate the slower speed of the DSP, the AD7634 acts as a slave
device, and data must be read after conversion. This mode also
allows the daisy-chain feature. The convert command could be
initiated in response to an internal timer interrupt.
The reading process can be initiated in response to the end-of-
conversion signal (BUSY going low) using an interrupt line of
the DSP. The serial peripheral interface (SPI) on the ADSP-219x
is configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, clock phase bit (CPHA) = 1, and SPI interrupt enable
(TIMOD) = 0 by writing to the SPI control register (SPICLTx).
It should be noted that to meet all timing requirements, the SPI
clock should be limited to 17 Mbps allowing it to read an ADC
result in less than 1.1 μs. When a higher sampling rate is desired,
use one of the parallel interface modes.
BUSY
CS
SDOUT
SDCLK
CNVST
AD7634*
PFx
SPIxSEL (PFx)
MISOx
SCKx
PFx OR TFSx
ADSP-219x*
*ADDITIONAL PINS OMITTED FOR CLARITY.
DVDD
MODE[1:0]
EXT/INT
RD
INVSCLK
06
40
6-
0
46
Figure 48. Interfacing the AD7634 to SPI Interface
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