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參數(shù)資料
| 型號(hào)： | AD7568BPZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/14頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT LC2MOS OCTAL 44PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 設(shè)置時(shí)間： | 500ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 17.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類(lèi)型： | 16 電流，單極；16 電流，雙極 |
| 采樣率（每秒）： | 2M |
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AD7568
–11–
PC5
PC6
PC7
SCK
MOSI
CLKIN
SDIN
CLR
LDAC
FSIN
68HC11*
AD7568*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7568 to 68HC11 Interface
In Figure 21, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7568 can be updated after each two-byte transfer, or else all
DACs can be simultaneously updated.
AD7568–ADSP-2101 Interface
Figure 22 shows a serial interface between the AD7568 and the
ADSP-2101 digital signal processor. The ADSP-2101 may be
set up to operate in the SPORT Transmit Normal Internal
Framing Mode. The following ADSP-2101 conditions are rec-
ommended: Internal SCLK; Active High Framing Signal; 16-bit
word length. Transmission is initiated by writing a word to the
TX register after the SPORT has been enabled. The data is then
clocked out on every rising edge of SCLK after TFS goes low.
TFS stays low until the next data transfer.
FO
TFS
DT
SCLK
CLKIN
SDIN
CLR
LDAC
FSIN
ADSP-2101*
AD7568*
*ADDITIONAL PINS OMITTED FOR CLARITY
+5V
Figure 22. AD7568 to ADSP-2101 Interface
AD7568–TMS320C25 Interface
Figure 23 shows an interface circuit for the TMS320C25
digital signal processor. The data on the DX pin is clocked
out of the processor’s Transmit Shift Register by the CLKX
signal. Sixteen-bit transmit format should be chosen by setting
the FO bit in the ST1 register to 0. The transmit operation be-
gins when data is written into the data transmit register of the
TMS320C25. This data will be transmitted when the FSX line
goes low while CLKX is high or going high. The data, starting
XF
FSX
DX
CLKX
CLKIN
SDIN
CLR
LDAC
FSIN
TMS320C25*
AD7568*
*ADDITIONAL PINS OMITTED FOR CLARITY
+5V
CLOCK
GENERATION
Figure 23. AD7568 to TMS320C25 Interface
with the MSB, is then shifted out to the DX pin on the rising
edge of CLKX. When all bits have been transmitted, the user
can update the DAC outputs by bringing the XF output flag low.
Multiple DAC Systems
If there are only two AD7568s in a system, there is a simple way
of programming each. This is shown in Figure 24. If the user
wishes to program one of the DACs in the first AD7568, then
DB3 of the serial bit stream should be set to 0, to correspond to
the state of the A0 pin on that device. If the user wishes to pro-
gram a DAC in the second AD7568, then DB3 should be set to
1, to correspond to A0 on that device.
FO
TFS
DT
SCLK
CLKIN
SDIN
CLR
LDAC
FSIN
ADSP-2101*
AD7568*
*ADDITIONAL PINS OMITTED FOR CLARITY
+5V
A0
CLKIN
SDIN
CLR
LDAC
FSIN
AD7568*
+5V
A0
Figure 24. Interfacing ADSP-2101 to Two AD7568s
REV. C
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| AD7568BS | 制造商:Analog Devices 功能描述:DAC 8-CH R-2R 12-bit 44-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:OCTAL 12-BIT DAC IC - Bulk 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Interface Ty |
| AD7568BS-REEL | 制造商:Analog Devices 功能描述:DAC 8-CH R-2R 12-bit 44-Pin MQFP T/R |
| AD7568BSZ | 功能描述:IC DAC 12BIT OCTAL LC2MOS 44MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類(lèi)型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AD7568BSZ-REEL | 功能描述:IC DAC 12BIT OCTAL LC2MOS 44MQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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