參數(shù)資料
型號: AD7538KRZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 15/16頁
文件大?。?/td> 0K
描述: IC DAC 14BIT W/BUFF 24-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標準包裝: 1,000
設(shè)置時間: 1.5µs
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 1W
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 24-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 24-SOIC W
包裝: 帶卷 (TR)
輸出數(shù)目和類型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 667k
AD7538
Rev. B | Page 8 of 16
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally
expressed in least significant bits or as a percentage of full-
scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s
in the DAC after the offset error has been adjusted out and is
expressed in least significant bits. Gain error is adjustable to
zero with an external potentiometer.
Digital-To-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state is called digital-to-
analog glitch impulse. This is normally specified as the area of
the glitch in either pA-secs or nV-secs depending upon whether
the glitch is measured as a current or voltage. It is measured
with VREF = AGND.
Output Capacitance
This is the capacitance from IOUT to AGND.
Output Leakage Current
Output leakage current is current which appears at IOUT with the
DAC register loaded to all 0s.
Multiplying Feedthrough Error
This is the ac error due to capacitive feedthrough from the VREF
terminal to IOUT with the DAC register loaded to all zeros.
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