參數(shù)資料
型號: AD7533JPZ
廠商: Analog Devices Inc
文件頁數(shù): 8/12頁
文件大?。?/td> 0K
描述: IC DAC 10BIT MULTIPLYING 20PLCC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 49
設(shè)置時間: 600ns
位數(shù): 10
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 30mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 20-PLCC(9x9)
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 1.7M
AD7533
Rev. C | Page 5 of 12
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for ideal zero and full scale and is expressed in % of
full-scale range or (sub) multiples of 1 LSB.
Resolution
Value of the LSB. For example, a unipolar converter with n bits
has a resolution of (2–n) (VREF). A bipolar converter of n bits has
a resolution of [2–(n–1)] (VREF). Resolution in no way implies
linearity.
Settling Time
Time required for the output function of the DAC to settle to
within LSB for a given digital input stimulus, that is, 0 to
full scale.
Gain Error
Gain error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error is adjusted out and is expressed in LSBs.
Gain error is adjustable to zero with an external potentiometer.
Feedthrough Error
Error caused by capacitive coupling from VREF to output with all
switches off.
Output Capacitance
Capacity from IOUT1 and IOUT2 terminals to ground.
Output Leakage Current
Current that appears on IOUT1 terminal with all digital inputs
low or on IOUT2 terminal when all inputs are high.
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