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參數(shù)資料
| 型號： | AD7533JPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT MULTIPLYING 20PLCC |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 49 |
| 設(shè)置時間： | 600ns |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 30mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 20-PLCC（9x9） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 1.7M |
AD7533
Rev. C | Page 7 of 12
CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
The AD7533 is a 10-bit multiplying DAC that consists of a
highly stable thin-film R-2R ladder and ten CMOS current
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage
or current reference.
The simplified D/A circuit is shown in Figure 7. An inverted
R- 2R ladder structure is used, that is, the binarily weighted
currents are switched between the IOUT1 and IOUT2 bus lines,
thus maintaining a constant current in each ladder leg
independent of the switch state.
20k
S1
S2
S3
SN
IOUT2
VREF
IOUT1
RFB
20k
10k
BIT 1 (MSB)
BIT 10 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
BIT 2
BIT 3
10k
20k
01134-
001
Figure 7. Functional Diagram
One of the CMOS current switches is shown in Figure 8. The
geometries of Device 1, Device 2, and Device 3 are optimized to
make the digital control inputs DTL/TTL/CMOS compatible
over the full military temperature range. The input stage drives
two inverters (Device 4, Device 5, Device 6, and Device 7),
which in turn drive the two output N channels. The on
resistances of the switches are binarily sealed so that the voltage
drop across each switch is the same. For example, Switch 1 in
Figure 8 is designed for an on resistance of 20 Ω, Switch 2 for
40 Ω, and so on. For a 10 V reference input, the current through
Switch 1 is 0.5 mA, the current through Switch 2 is 0.25 mA,
and so on, thus maintaining a constant 10 mV drop across each
switch. It is essential that each switch voltage drop be equal if
the binarily weighted current division property of the ladder is
to be maintained.
DTL/TTL/
CMOS
INPUT
V+
13
2
TO LADDER
5
4
250
7
6
89
IOUT1
IOUT2
01
13
4-
0
07
Figure 8. CMOS Switch
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs high and digital
all digital inputs low, the reference current is switched to IOUT2.
The current source ILEAKAGE is composed of surface and junction
leakages to the substrate, while the I/1024 current source represents
a constant 1-bit current drain through the termination resistor
on the R-2R ladder. The on capacitance of the output N channel
switch is 100 pF, as shown on the IOUT2 terminal. The off switch
capacitance is 35 pF, as shown on the IOUT1 terminal. Analysis of
the circuit for all digital inputs high, as shown in Figure 10, is
similar to Figure 9; however, the on switches are now on
Terminal IOUT1. Therefore, there is the 100 pF at that terminal.
IOUT2
IOUT1
VREF
IREF
RFB
ILEAKAGE
R
011
34
-00
8
R
10k
100pF
ILEAKAGE
35pF
I/1024
Figure 9. Equivalent Circuit—All Digital Inputs Low
IOUT2
IOUT1
VREF
IREF
RFB
ILEAKAGE
R
01
13
4-
0
9
R
100pF
ILEAKAGE
35pF
I/1024
R
10k
Figure 10. Equivalent Circuit—All Digital Inputs High
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7533JPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS Low Cost, 10-Bit Multiplying DAC |
| AD7533JPZ-REEL | 功能描述:IC DAC 10BIT MULTIPLYING 20PLCC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AD7533JR | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS LOW COST 10-BIT MULTIPLYING DAC |
| AD7533KCWE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10-Bit Digital-to-Analog Converter |
| AD7533KD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Converter IC |
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