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參數(shù)資料
| 型號(hào)： | AD7492ARU-5 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS |
| 中文描述： | 抗輻射高效，5安培開關(guān)穩(wěn)壓器 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 194K |
| 代理商： | AD7492ARU-5 |
REV. 0
AD7492
–9–
CODE
1
0
–
1
0
4089
–
0.8
3578
3067
2556
2045
1534
1023
512
–
0.6
–
0.4
–
0.2
0.2
0.4
0.6
0.8
TPC 7. Typical INL for 2.75 V @ 25
°
C
CODE
1
0
–
1
0
4089
–
0.8
3578
3067
2556
2045
1534
1023
512
–
0.6
–
0.4
–
0.2
0.2
0.4
0.6
0.8
TPC 8. Typical DNL for 2.75 V @ 25
°
C
CIRCUIT DESCRIPTION
CONVERTER OPERATION
The AD7492 is a 12-bit successive approximation analog-to-
digital converter based around a capacitive DAC. The AD7492
can convert analog input signals in the range 0 V to V
REF
. Figure 2
shows a very simplified schematic of the ADC. The Control
Logic, SAR, and the Capacitive DAC are used to add and sub-
tract fixed amounts of charge from the sampling capacitor to
bring the comparator back into a balanced condition.
CAPACITIVE
DAC
SWITCHES
SAR
CONTROL LOGIC
COMPARATOR
OUTPUT DATA
12-BIT PARALLEL
V
IN
V
REF
CONTROL
INPUTS
Figure 2. Simplified Block Diagram of AD7492
Figure 3 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A. The comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on V
IN
.
COMPARATOR
V
IN
CONTROL LOGIC
CAPACITIVE
DAC
AGND
2k
SW2
SW1
A
B
Figure 3. ADC Acquisition Phase
Figure 4 shows the ADC during conversion. When conversion
starts, SW2 will open and SW1 will move to Position B, causing
the comparator to become unbalanced. The ADC then runs
through its successive approximation routine and brings the com-
parator back into a balanced condition. When the comparator is
rebalanced, the conversion result is available in the SAR register.
COMPARATOR
V
IN
CONTROL LOGIC
CAPACITIVE
DAC
AGND
2k
SW2
SW1
A
B
Figure 4. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7492.
Conversion is initiated by a falling edge on
CONVST
. Once
CONVST
goes low the BUSY signal goes high, and at the end
of conversion the falling edge of BUSY is used to activate an
Interrupt Service Routine. The
CS
and
RD
lines are then activated
in parallel to read the 12 data bits. The internal bandgap reference
voltage is 2.5 V, providing an analog input range of 0 V to 2.5 V,
making the AD7492 a unipolar A/D. A capacitor with a mini-
mum capacitance of 100 nF is needed at the output of the REF
OUT pin as it stabilizes the internal reference value. It is recom-
mended to perform a dummy conversion after power-up as the
first conversion result could be incorrect. This also ensures that
the part is in the correct mode of operation. The
CONVST
pin
should not be floating when power is applied as a rising edge on
CONVST
might not wake up the part.
In Figure 5 the V
DRIVE
pin is tied to DV
DD
,
which results in logic
output voltage values being either 0 V or DV
DD
. The voltage
applied to V
DRIVE
controls the voltage value of the output logic
signals and the input logic signals. For example, if DV
DD
is
supplied by a 5 V supply and V
DRIVE
by a 3 V supply, the logic
output voltage levels would be either 0 V or 3 V. This feature
allows the AD7492 to interface to 3 V parts while still enabling
the A/D to process signals at 5 V supply.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7492ARU-5-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1.25MSPS 12-BIT PARALLEL 24TSSOP - Tape and Reel |
| AD7492ARU-5-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1.25Msps 12-bit Parallel 24-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1.25MSPS 12-BIT PARALLEL 24TSSOP - Tape and Reel |
| AD7492ARU-REEL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Parallel 24-Pin TSSOP T/R |
| AD7492ARU-REEL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 12-bit Parallel 24-Pin TSSOP T/R 制造商:Analog Devices 功能描述:ADC SGL SAR 1MSPS 12-BIT PARALLEL 24TSSOP - Tape and Reel |
| AD7492ARUZ | 功能描述:IC ADC 12BIT REF/CLOCK 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁面:1156 (CN2011-ZH PDF) 其它名稱:497-5435-6 |
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