參數(shù)資料
型號(hào)： AD7492ARU-5
元件分類(lèi)： 基準(zhǔn)電壓源/電流源
英文描述： RADIATION HARDENED HIGH EFFICIENCY, 5 AMP SWITCHING REGULATORS
中文描述： 抗輻射高效，5安培開(kāi)關(guān)穩(wěn)壓器
文件頁(yè)數(shù)： 3/16頁(yè)
文件大小： 194K
代理商： AD7492ARU-5
REV. 0
–3–
AD7492
AD7492–SPECIFICATIONS
1
(V
DD
= 2.7 V to 5.25 V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Parameter
A Version
1
B Version
1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal to Noise + Distortion (SINAD)
f
S
= 1 MSPS
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
69
68
70
68
–85
–87
–75
–86
–90
–76
69
68
70
68
–85
–87
–75
–86
–90
–76
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB max
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second Order Terms
–77
–90
–69
–88
5
15
10
–77
–90
–69
–88
5
15
10
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
f
IN
= 500 kHz Sine Wave
f
IN
= 100 kHz Sine Wave
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
f
S
= 1 MSPS
12
±
1.5
12
Bits
LSB max
LSB typ
LSB max
LSB max
±
0.6
±
1
+1.5/–0.9
V
DD
= 5 V
V
DD
= 3 V
Guaranteed No Missed Codes to
12 Bits (A and B Version)
Differential Nonlinearity
+1.5/–0.9
Offset Error
Gain Error
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
REFERENCE OUTPUT
REF OUT Output Voltage Range
LOGIC INPUTS
Input High Voltage, V
INH2
Input Low Voltage, V
INL2
Input Current, I
IN
Input Capacitance, C
IN3
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode
Quiescent Current
Partial Sleep Mode
Full Sleep Mode
Power Dissipation
4
Normal Mode
Partial Sleep Mode
Full Sleep Mode
±
9
±
2.5
±
9
±
2.5
LSB max
LSB max
0 to 2.5
±
1
33
0 to 2.5
±
1
33
V
μ
A max
pF typ
2.5
2.5
V
±
1.5% for Specified Performance
V
DRIVE
×
0.7
V
DRIVE
×
0.3
±
1
10
V
DRIVE
×
0.7
V
DRIVE
×
0.3
±
1
10
V min
V max
μ
A max
pF max
V
DD
= 5 V
±
5%
V
DD
= 5 V
±
5%
Typically 10 nA, V
IN
= 0 V or V
DD
V
DRIVE
– 0.2
0.4
±
10
10
Straight (Natural) Binary
V
DRIVE
– 0.2
0.4
±
10
10
Straight (Natural) Binary
V min
V max
μ
A max
pF max
I
SOURCE
= 200
μ
A
I
SINK
= 200
μ
A
880
120
1
880
120
1
ns max
ns min
MSPS max
Conversion Time + Acquisition Time
2.7/5.25
2.7/5.25
V min/max
Digital I/Ps = 0 V or DV
DD.
f
S
= 1 MSPS, Typ 2.2 mA
3
1.8
250
1
3
1.8
250
1
mA max
mA max
μ
A max
μ
A max
Static. Typ 190
μ
A
Static. Typ 200 nA
Digital I/Ps = 0 V or DV
DD
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 5 V
15
1.25
5
15
1.25
5
mW max
mW max
μ
W max
NOTES
1
Temperature ranges as follows: A and B Versions: –40
°
C to +85
°
C.
2
V
INH
and V
INL
trigger levels are set by the V
DRIVE
voltage. The logic interface circuitry is powered by V
DRIVE
.
3
Sample tested @ 25
°
C to ensure compliance.
4
See Power vs. Throughput Rate section.
Specifications subject to change without notice.
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