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AD7482
Rev. B | Page 13 of 20
For higher input bandwidth applications, t
he AD8021 op amp
(also available as a dua
l AD8022 op amp) is the recommended
choice to drive the AD7482.
Figure 15 shows the analog input
circuit used to obtain the data for the FFT plot shown
in Figure 4. A
bipolar analog signal is applied to the terminal and biased up with a
stable, low noise dc voltage connected, as shown i
n Figure 12. A
10 pF compensation capacitor is connected between Pin 5 of the
+12 V and 12 V supplies. The supply pins are decoupled as close
to the device as possible, with both a 0.1 μF and
a 10 μF capacitor
connected to each pin. In each case, the 0.1 μF capacitor should
be the closer of the two caps to the device. Th
e AD8021 logic
reference pin is tied to analog ground and the DISABLE
ADC TRANSFER FUNCTION
Pin is
tied to the positive supply, as shown i
n Figure 12. Detailed
The output coding of the AD7482 is straight binary. The designed
code transitions occur midway between the successive integer
LSB values, that is, 1/2 LSB, 3/2 LSB, and so on. The LSB size is
VREF/4096. The nominal transfer characteristic for the AD7482 is
shown i
n Figure 16. This transfer characteristic may be shifted
000...000
0V
ADC
CO
DE
ANALOG INPUT
111...111
000...001
000...010
111...110
111...000
011...111
0.5LSB
+VREF – 1.5LSB
1LSB = VREF/4096
02638-
016
Figure 16. AD7482 Transfer Characteristic
POWER SAVING
The AD7482 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. In addition, the
AD7482 features two power saving modes, nap and standby. These
modes are selected by bringing either the NAP pin or STBY pin
to a logic high, respectively.
When operating the AD7482 in normal fully powered mode,
the current consumption is 18 mA during conversion and the
quiescent current is 12 mA. Operating at a throughput rate of
1 MSPS, the conversion time of 300 ns contributes 27 mW to
the overall power dissipation.
(300 ns/1 μs) × (5 V × 18 mA) = 27 mW
For the remaining 700 ns of the cycle, the AD7482 dissipates
42 mW of power.
(700 ns/1 μs) × (5 V × 12 mA) = 42 mW
Therefore, the power dissipated during each cycle is
27 mW + 42 mW = 69 mW
Figure 17 shows the AD7482 conversion sequence operating in
normal mode.
CONVST
BUSY
300ns
1s
700ns
02638-
017
Figure 17. Normal Mode Power Dissipation
In nap mode, almost all the internal circuitry is powered down.
In this mode, the power dissipation is reduced to 2.5 mW. When
using an external reference, there must be a minimum of 300 ns
from exiting nap mode to initiating a conversion. This is necessary
to allow the internal circuitry to settle after power-up and for
the track-and-hold to properly acquire the analog input signal.
The internal reference cannot be used in conjunction with the
nap mode.
If the AD7482 is put into nap mode after each conversion, the
average power dissipation is reduced, but the throughput rate is
limited by the power-up time. Using the AD7482 with a through-
put rate of 500 kSPS while placing the part in nap mode after
each conversion results in average power dissipation as follows:
The power-up phase contributes
(300 ns/2 μs) × (5 V × 12 mA) = 9 mW
The conversion phase contributes
(300 ns/2 μs) × (5 V × 18 mA) = 13.5 mA
While in nap mode for the rest of the cycle, the AD7482
dissipates only 1.75 mW of power.
(1400 ns/2 μs) × (5 V × 0.5 mA) = 1.75 mW
Therefore, the power dissipated during each cycle is
9 mW + 13.5 mW + 1.75 mW = 24.25 mW