V
參數(shù)資料
型號: AD7482BSTZ
廠商: Analog Devices Inc
文件頁數(shù): 21/21頁
文件大?。?/td> 0K
描述: IC ADC 12BIT SAR 3MSPS 48-LQFP
標準包裝: 1
位數(shù): 12
采樣率(每秒): 3M
數(shù)據(jù)接口: 并聯(lián)
轉換器數(shù)目: 1
功率耗散(最大): 90mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 托盤
輸入數(shù)目和類型: 1 個單端,單極
產(chǎn)品目錄頁面: 778 (CN2011-ZH PDF)
AD7482
Rev. B | Page 8 of 20
Pin No.
Mnemonic
Description
30, 31
DGND
Ground Reference for Digital Circuitry.
32
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface logic of
the device operates.
40
D12
Data Output Bit for Overranging. If the overrange feature is not used, this pin should be pulled to DGND via a
100 k resistor.
41
CONVST
Convert Start Logic Input. A conversion is initiated on the falling edge of the CONVST signal. The input track-
and-hold amplifier goes from track mode to hold mode, and the conversion process commences.
42
RESET
Reset Logic Input. An active low reset pulse must be applied to this pin after power-up to ensure correct
operation. A falling edge on this pin resets the internal state machine and terminates a conversion that
may be in progress. The contents of the offset register are also cleared on this edge. Holding this pin low
keeps the part in a reset state.
43
MODE2
Operating Mode Logic Input. See Table 8 for details.
44
MODE1
Operating Mode Logic Input. See Table 8 for details.
45
CLIP
Logic Input. A logic high on this pin enables output clipping. In this mode, any input voltage that is greater
than positive full scale or less than negative full scale is clipped to all 1s or all 0s, respectively. Further details
are given in the Offset/Overrange section.
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