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參數資料
| 型號： | AD7478WARTZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 10/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 8BIT 1MSPS SOT23-6 |
| 標準包裝： | 1 |
| 位數： | 8 |
| 采樣率（每秒）： | 1M |
| 數據接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 17.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應商設備封裝： | SOT-23-6 |
| 包裝： | 標準包裝 |
| 輸入數目和類型： | 1 個單端，單極 |
| 產品目錄頁面： | 778 (CN2011-ZH PDF) |
| 其它名稱： | AD7478WARTZ-RL7DKR |
AD7476/AD7477/AD7478
Rev. F | Page 17 of 24
Power-Up Time
The power-up time of the AD7476/AD7477/AD7478 is typi-
cally 1 μs, which means that with any frequency of SCLK up to
20 MHz, one dummy cycle is always sufficient to allow the
device to power up. Once the dummy cycle is complete, the
ADC is fully powered up and the input signal is acquired
properly. The quiet time (tQUIET) must still be allowed from the
point at which the bus goes back into three-state (after the
dummy conversion), to the next falling edge of CS. When
running at 1 MSPS throughput rate, the AD7476/AD7477/
AD7478 powers up and acquires a signal within ±0.5 LSB in
one dummy cycle, such as 1 μs.
When powering up from the power-down mode with a dummy
cycle, as shown in Figure 21, the track-and-hold, that was in
hold mode while the part was powered down, returns to track
mode after the first SCLK edge the part receives after the falling
edge of CS. This is shown as Point A in
. Although at
any SCLK frequency, one dummy cycle is sufficient to power up
the device and acquire VIN, this does not necessarily mean that a
full dummy cycle of 16 SCLKs must always elapse to power up
the device and fully acquire VIN; 1 μs is sufficient to power up
the device and acquire the input signal. If, for example, a 5 MHz
SCLK frequency is applied to the ADC, the cycle time is 3.2 μs.
In one dummy cycle, 3.2 μs, the part is powered up and VIN is
fully acquired. However, after 1 μs with a 5 MHz SCLK, only
five SCLK cycles elapse. At this stage, the ADC is fully powered
up and the signal acquired. In this case, the
CS can be brought
high after the tenth SCLK falling edge and brought low again
after a time, tQUIET, to initiate the conversion.
When power supplies are first applied to the AD7476/AD7477/
AD7478, the ADC may power up in either power-down mode
or normal mode. Allow a dummy cycle to elapse to ensure the
part is fully powered up before attempting a valid conversion.
Likewise, to keep the part in the power-down mode while not
in use and then to power up the part in power-down mode, use
the dummy cycle to ensure the device is in power-down by
executing a cycle such as that shown in Figure 20. Once supplies
are applied to the AD7476/AD7477/AD7478, the power-up
time is the same when powering up from the power-down
mode. It takes approximately 1 μs to fully power up if the part
powers up in normal mode. It is not necessary to wait 1 μs
before executing a dummy cycle to ensure the desired mode of
operation. Instead, the dummy cycle can occur directly after
power is supplied to the ADC. If the first valid conversion is
then performed directly after the dummy conversion, ensure
that adequate acquisition time has been allowed.
When powering up from power-down mode, the part returns to
track upon the first SCLK edge applied after the falling edge of
CS. However, when the ADC powers up initially after supplies
are applied, the track-and-hold is already in track.
This means that if the ADC powers up in the desired mode of
operation, and a dummy cycle is not required to change mode,
then a dummy cycle is not required to place the track-and-hold
into track.
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7476/AD7477/
AD7478 when not converting, the average power consumption
of the ADC decreases at lower throughput rates. Figure 22
shows that as the throughput rate reduces, the device remains in
its power-down state longer, and the average power
consumption over time drops accordingly.
For example, if the AD7476/AD7477/AD7478 operates in
continuous sampling mode with a throughput rate of 100 kSPS
and a SCLK of 20 MHz (VDD = 5 V), and the device is placed in
the power-down mode between conversions, then the power
consumption is calculated as follows. The power dissipation
during normal operation is 17.5 mW (VDD = 5 V). If the power-
up time is one dummy cycle, such as 1 μs, and the remaining
conversion time is another cycle, such as 1 μs, then the part is
said to dissipate 17.5 mW for 2 μs during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 μs and
the average power dissipated during each cycle is
(2/10) × (17.5 mW) = 3.5 mW. If VDD = 3 V, SCLK = 20 MHz,
and the device is again in power-down mode between conver-
sions, the power dissipation during normal operation is
4.8 mW.
The AD7476/AD7477/AD7478 can now be said to dissipate
4.8 mW for 2 μs during each conversion cycle. With a through-
put rate of 100 kSPS, the average power dissipated during each
cycle is (2/10) × (4.8 mW) = 0.96 mW. Figure 22 shows the
power vs. throughput rate when using the power-down mode
between conversions with both 5 V and 3 V supplies.
100
0.01
0.1
1
10
0
350
300
250
200
150
100
50
01
02
4-
02
2
PO
W
E
R
(mW
)
THROUGHPUT RATE (kSPS)
VDD = 5V, SCLK = 20MHz
VDD = 3V, SCLK = 20MHz
Figure 22. Power vs. Throughput Rate
Power-down mode is intended for use with throughput rates of
approximately 333 kSPS and under. At higher sampling rates,
power is not saved by using power-down mode.
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