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參數(shù)資料
| 型號： | AD7450A |
| 英文描述： | AD7450A/AD7440: Differential Input. 1MSPS. 12-Bit ADC in 8-lead SOT-23 Preliminary Data Sheet (Rev. PrF. 3/03) |
| 中文描述： | AD7450A/AD7440：差分輸入。 1MSPS。 12位ADC，采用8引腳SOT - 23的初步數(shù)據(jù)（牧師脈沖重復(fù)頻率。3 / 03） |
| 文件頁數(shù)： | 22/24頁 |
| 文件大小： | 914K |
| 代理商： | AD7450A |
REV. PrF
PRELIMINARY TECHNICAL DATA
–22–
AD7450A/AD7440
ITFS = 1.
To implement the power-down mode SLEN should be set
to 1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 25. The
ADSP21xx has the TFS and RFS of the SPORT tied
together, with TFS set as an output and RFS set as an
input. The DSP operates in Alternate Framing Mode and
the SPORT control register is set up as described. The
Frame Synchronisation signal generated on the TFS is
tied to
CS
and as with all signal processing applications
equidistant sampling is necessary. However, in this ex-
ample, the timer interrupt is used to control the sampling
rate of the ADC and under certain conditions, equidistant
sampling may not be acheived.
AD7450A/AD7440*
SCLK
SDATA
SCLK
DR
RFS
TFS
ADSP21xx*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. Interfacing to the ADSP 21xx
The timer registers etc., are loaded with a value which
will provide an interrupt at the required sample interval.
When an interrupt is received, a value is transmitted with
TFS/DT (ADC control word). The TFS is used to con-
trol the RFS and hence the reading of data. The frequency
of the serial clock is set in the SCLKDIV register. When
the instruction to transmit with TFS is given, (i.e.
AX0=TX0), the state of the SCLK is checked. The DSP
will wait until the SCLK has gone High, Low and High
before transmission will start. If the timer and SCLK val-
ues are chosen such that the instruction to transmit occurs
on or near the rising edge of SCLK, then the data may be
transmitted or it may wait until the next clock edge.
For example, the ADSP-2111 has a master clock fre-
quency of 16MHz. If the SCLKDIV register is loaded
with the value 3 then a SCLK of 2MHz is obtained, and 8
master clock periods will elapse for every 1 SCLK period.
If the timer registers are loaded with the value 803, then
100.5 SCLKs will occur between interrupts and subse-
quently between transmit instructions. This situation will
result in non-equidistant sampling as the transmit instruc-
tion is occuring on a SCLK edge. If the number of
SCLKs between interrupts is a whole integer figure of N
then equidistant sampling will be implemented by the
DSP.
AD7450A/AD7440 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a
continuous serial clock and frame synchronization signals
to synchronize the data transfer operations with peripheral
devices like the AD7450A/AD7440. The
CS
input allows
easy interfacing between the TMS320C5x/C54x and the
AD7450A/AD7440 without any glue logic required. The
serial port of the TMS320C5x/C54x is set up to operate
in burst mode with internal CLKX (TX serial clock) and
FSX (TX frame sync). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1,
MCM = 1 and TXM = 1. The format bit, FO, may be set
to 1 to set the word length to 8-bits, in order to imple-
ment the power-down mode on the AD7450A/AD7440.
The connection diagram is shown in Figure 26. It should
be noted that for signal processing applications, it is im-
perative that the frame synchronisation signal from the
TMS320C5x/C54x will provide equidistant sampling.
AD7450A/AD7440*
SDATA
CLKX
FSR
TMS320C5x/C54x*
*ADDITIONAL PINS OMITTED FOR CLARITY
CLKR
DR
FSX
Figure 26. Interfacing to the TMS320C5x/C54x
AD7450A/AD7440 to DSP56xxx
The connection diagram in figure 27 shows how the
AD7450A/AD7440 can be connected to the SSI (Synchro-
nous Serial Interface) of the DSP56xxx family of DSPs
from Motorola. The SSI is operated in Synchronous
Mode (SYN bit in CRB =1) with internally generated 1-
word frame sync for both Tx and Rx (bits FSL1 =0 and
FSL0 =0 in CRB). Set the word length to 16 by setting
bits WL1 =1 and WL0 = 0 in CRA. To implement the
power-down mode on the AD7450A/AD7440 then the
word length can be changed to 8 bits by setting bits WL1
= 0 and WL0 = 0 in CRA. It should be noted that for
signal processing applications, it is imperative that the
frame synchronisation signal from the DSP56xxx will
provideequidistant sampling.
AD7450A/AD7440*
SDATA
*
*ADDITIONAL PINS OMITTED FOR CLARITY
SRD
SCLK
SCLK
SR2
DSP56xxx*
Figure 27. Interfacing to the DSP56xx
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