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參數(shù)資料
| 型號： | AD7450A |
| 英文描述： | AD7450A/AD7440: Differential Input. 1MSPS. 12-Bit ADC in 8-lead SOT-23 Preliminary Data Sheet (Rev. PrF. 3/03) |
| 中文描述： | AD7450A/AD7440：差分輸入。 1MSPS。 12位ADC，采用8引腳SOT - 23的初步數(shù)據(jù)（牧師脈沖重復(fù)頻率。3 / 03） |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AD7450A |
REV. PrF
PRELIMINARY TECHNICAL DATA
–18–
AD7450A/AD7440
The value of the reference sets the analog input span and
the common mode voltage range. Errors in the reference
source will result in gain errors in the AD7450A/AD7440
transfer function and will add to specified full scale errors
on the part. A capacitor of 0.1μF should be used to
decouple the V
REF
pin to GND.
Table I lists examples of suitable voltage references that
could be used that are available from Analog Devices and
Figure 18 shows a typical connection diagram for the
V
REF
pin.
Table I Examples of Suitable Voltage References
Reference Output Initial
Voltage Accuracy Current
(% max)
Operating
(
μ
A)
REF192 2.5
REF43 2.5
AD780 2.5
0.08-0.4
0.06-0.1
0.04-0.2
45
600
1000
VREF
AD7450/
AD7440*
VDD
1
2
3
4
5
6
7
8
VIN
Temp
GND
Trim
Vout
OpSel
0.1μF
NC
NC
NC
NC
VDD
0.1μF
0.1μF
10nF
*ADDITIONAL PINS OMITTED FOR CLARITY
AD780
2.5 V
Figure 18. Typical V
REF
Connection Diagram for V
DD
= 5 V
SINGLE ENDED OPERATION
When supplied with a 5 V power supply, the AD7450A/
AD7440 can handle a single ended input. The design of
this part is optimized for differential operation so with a
single ended input, performance will degrade. Linearity
will degrade by typically 0.2 LSBs, Zero Code and the
Full Scale Errors will degrade by typically 2 LSBs and
AC performance is not guaranteed.
To operate the AD7450A/AD7440 in single ended mode,
the V
IN+
input is coupled to the signal source while the
V
IN-
input is biased to the appropriate voltage correspond-
ing to the mid-scale code transition. This voltage is the
Common Mode, which is a fixed dc voltage (usually the
reference). The V
IN+
input swings around this value and
should have voltage span of 2 x V
REF
to make use of the
full dynamic range of the part. The input signal will there-
fore have peak to peak values of Common Mode ±V
REF
.
If the analog input is unipolar then an opamp in a non-
inverting unity gain configuration can be used to drive the
V
IN+
pin. Because the ADC operates from a single supply,
it will be necessary to level shift ground based bipolar
signals to comply with the input requirements. An
opamp can be configured to rescale and level shift the
ground based bipolar signal so it is compatible with the
selected input range of the AD7450A/AD7440 (see Figure
19).
EXTERNAL
VREF(2.5V)
VIN
0V
+2.5V
-2.5V
0.1μF
VREF
VIN+
AD7450/
AD7440
VIN-
R
R
R
R
0V
+2.5V
+5V
Figure 19. Applying a Bipolar Single Ended Input to the
AD7450A/AD7440
SERIAL INTERFACE
Figures 1 and 2 show detailed timing diagrams for the
serial interface of the AD7450A and the AD7440 respec-
tively. The serial clock provides the conversion clock and
also controls the transfer of data from the device during
conversion.
CS
initiates the conversion process and frames
the data transfer. The falling edge of
CS
puts the track
and hold into hold mode and takes the bus out of three-
state. The analog input is sampled and the conversion
initiated at this point. The conversion will require 16
SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track and
hold will go back into track on the next SCLK rising edge
as shown at point B in Figures 1 and 2. On the 16th
SCLK falling edge the SDATA line will go back into
three-state. If the rising edge of
CS
occurs before 16
SCLKs have elapsed, the conversion will be terminated
and the SDATA line will go back into three-state.
The conversion result from the AD7450A/AD7440 is pro-
vided on the SDATA output as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input. The
data stream of the AD7450A consists of four leading zeros,
followed by 12 bits of conversion data which is provided MSB
first; the data stream of the AD7440 consists of four leading
zeros, followed by the 10 bits of conversion data, followed
by two trailing zeros, which is also provided MSB first. In
both cases, the output coding is twos complement.
16 serial clock cycles are required to perform a conversion
and to access data from the AD7450A/AD7440.
CS
going
low provides the first leading zero to be read in by the micro-
controller or DSP. The remaining data is then clocked out
on the subsequent SCLK falling edges beginning with the
second leading zero. Thus the first falling clock edge on the
serial clock provides the second leading zero. The final bit
in the data transfer is valid on the 16th falling edge, having
been clocked out on the previous (15th) falling edge. Once
the conversion is complete and the data has been accessed
after the 16 clock cycles, it is important to ensure that, before
the next conversion is initiated, enough time is left to meet
the acquisition and quiet time specifications - see the Timing
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