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參數(shù)資料
| 型號： | AD744KR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Precision, 500 ns Settling BiFET Op Amp |
| 中文描述： | OP-AMP, 1000 uV OFFSET-MAX, 13 MHz BAND WIDTH, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 21/24頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AD744KR |
REV. PrF
PRELIMINARY TECHNICAL DATA
–21–
AD7450A/AD7440
SCLK edge applied after the falling edge of
CS
. How-
ever, when the ADC powers up initially after supplies are
applied, the track and hold will already be in track. This
means if (assuming one has the facility to monitor the
ADC supply current) the ADC powers up in the desired
mode of operation and thus a dummy cycle is not required
to change mode, then neither is a dummy cycle required
to place the track and hold into track.
POWER VERSUS THROUGHPUT RATE
By using the power-down mode on the AD7450A/AD7440
when not converting, the average power consumption of
the ADC decreases at lower throughput rates. Figure 24
shows how, as the throughput rate is reduced, the device
remains in its power-down state longer and the average
power consumption reduces accordingly. It shows this for
both 5V and 3V power supplies.
For example, if the AD7450A/AD7440 is operated in
continuous sampling mode with a throughput rate of
100kSPS and an SCLK of 18MHz and the device is
placed in the power down mode between conversions, then
the power consumption is calculated as follows:
Power dissipation during normal operation = 9mW typ
(for V
DD
= 5V).
If the power up time is 1 dummy cycle i.e. 1μsec, and the
remaining conversion time is another cycle i.e. 1μsec, then
the AD7450A/AD7440 can be said to dissipate 9mW for
2μsec* during each conversion cycle.
If the throughput rate = 100kSPS then the cycle time =
10μsec and the average power dissipated during each cycle
is:
(2/10) x 9mW = 1.8mW
For the same scenario, if V
DD
= 3V, the power dissipation
during normal operation is 3.75mW max.
The AD7450A/AD7440 can now be said to dissipate
3.75mW for 2μsec* during each conversion cycle.
The average power dissipated during each cycle with a
throughput rate of 100kSPS is therefore:
(2/10) x 3.75mW = 0.75mW
This is how the power numbers in Figure 24 are calcu-
lated.
For throughput rates above 320kSPS, it is recommended
that for optimum power performance, the serial clock
frequency is reduced.
0
50
100
150
200
250
300
350
THROUGHPUT (kSPS)
V
DD
= 5V
V
DD
= 3V
0.01
0.1
1
10
100
Figure 24. Power versus Throughput Rate for Power Down
Mode
*This figure assumes a very short time used to enter the power down
mode. This will increase as the burst of clocks used to enter the
power down mode is increased.
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7450A/AD7440 allows the
part to be directly connected to a range of different micro-
processors. This section explains how to interface the
AD7450A/AD7440 with some of the more common
microcontroller and DSP serial interface protocols.
AD7450A/AD7440 to ADSP21xx
The ADSP21xx family of DSPs are interfaced directly to
the AD7450A/AD7440 without any glue logic required.
The SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data words
ISCLK = 1, Internal serial clock
TFSR = RFSR = 1, Frame every word
IRFS = 0,
Figure 23. Exiting Power Down Mode
SDATA
INVALID DATA
SCLK
1
16
VALID DATA
1
A
THE PART BEGINS
TO POWER UP
THE PART IS FULLY POWERED
UP WITH VIN FULLY ACQUIRED
10
10
16
tPOWERUP
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