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參數(shù)資料
| 型號(hào)： | AD744KR |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Precision, 500 ns Settling BiFET Op Amp |
| 中文描述： | OP-AMP, 1000 uV OFFSET-MAX, 13 MHz BAND WIDTH, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AD744KR |
REV. PrF
PRELIMINARY TECHNICAL DATA
–20–
AD7450A/AD7440
4 LEADING ZEROS + CONVERSION RESULT
SDATA
10
16
SCLK
1
Figure 21. Normal Mode Operation
Power Down Mode
This mode is intended for use in applications where
slower throughput rates are required; either the ADC is
powered down between each conversion, or a series of
conversions may be performed at a high throughput rate
and the ADC is then powered down for a relatively long
duration between these bursts of several conversions.
When the AD7450A/AD7440 is in the power down mode,
all analog circuitry is powered down. To enter power
down mode, the conversion process must be interrupted by
bringing
CS
high anywhere after the second falling edge
of SCLK and before the tenth falling edge of SCLK as
shown in Figure 22.
THREE STATE
SCLK
SDATA
1
2
10
Figure 22. Entering Power Down Mode
Once
CS
has been brought high in this window of
SCLKs, the part will enter power down and the conver-
sion that was initiated by the falling edge of
CS
will be
terminated and SDATA will go back into three-state.
The time from the rising edge of
CS
to SDATA three-
state enabled will never be greater than t
8
(see the
‘Timing Specifications’). If
CS
is brought high before
the second SCLK falling edge, the part will remain in
normal mode and will not power-down. This will avoid
accidental power-down due to glitches on the
CS
line.
In order to exit this mode of operation and power the
AD7450A/AD7440 up again, a dummy conversion is per-
formed. On the falling edge of
CS
the device will begin
to power up, and will continue to power up as long as
CS
is held low until after the falling edge of the 10th SCLK.
The device will be fully powered up after 1μsec has
elapsed and, as shown in Figure 23, valid data will result
from the next conversion.
If
CS
is brought high before the 10th falling edge of
SCLK, the AD7450A/AD7440 will again go back into
power-down. This avoids accidental power-up due to
glitches on the
CS
line or an inadvertent burst of eight
SCLK cycles while
CS
is low. So although the device
may begin to power up on the falling edge of
CS
, it will
again power-down on the rising edge of
CS
as long as it
occurs before the 10th SCLK falling edge.
Power up Time
The power up time of the AD7450A/AD7440 is typically
1μsec, which means that with any frequency of SCLK up
to 18MHz, one dummy cycle will always be sufficient to
allow the device to power-up. Once the dummy cycle is
complete, the ADC will be fully powered up and the input
signal will be acquired properly. The quiet time t
QUIET
must still be allowed from the point at which the bus goes
back into three-state after the dummy conversion, to the
next falling edge of
CS
.
When running at the maximum throughput rate of
1MSPS, the AD7450A/AD7440 will power up and ac-
quire a signal within ±0.5LSB in one dummy cycle, i.e.
1μs. When powering up from the power-down mode with
a dummy cycle, as in Figure 23, the track and hold, which
was in hold mode while the part was powered down, re-
turns to track mode after the first SCLK edge the part
receives after the falling edge of
CS
. This is shown as
point A in Figure 23.
Although at any SCLK frequency one dummy cycle is
sufficient to power the device up and acquire V
IN
, it does
not necessarily mean that a full dummy cycle of 16
SCLKs must always elapse to power up the device and
acquire V
IN
fully; 1μs will be sufficient to power the de-
vice up and acquire the input signal.
For example, if a 5MHz SCLK frequency was applied to
the ADC, the cycle time would be 3.2μs (i.e. 1/(5MHz) x
16). In one dummy cycle, 3.2μs, the part would be pow-
ered up and V
IN
acquired fully. However after 1μs with a
5MHz SCLK only 5 SCLK cycles would have elapsed. At
this stage, the ADC would be fully powered up and the
signal acquired. So, in this case the
CS
can be brought
high after the 10th SCLK falling edge and brought low
again after a time t
QUIET
to initiate the conversion.
When power supplies are first applied to the AD7450A/
AD7440, the ADC may either power up in the power-
down mode or normal mode. Because of this, it is best to
allow a dummy cycle to elapse to ensure the part is fully
powered up before attempting a valid conversion. Like-
wise, if the user wishes the part to power up in
power-down mode, then the dummy cycle may be used to
ensure the device is in power-down by executing a cycle
such as that shown in Figure 22.
Once supplies are applied to the AD7450A/AD7440, the
power up time is the same as that when powering up from
the power-down mode. It takes approximately 1μs to
power up fully if the part powers up in normal mode. It is
not necessary to wait 1μs before executing a dummy cycle
to ensure the desired mode of operation. Instead, the
dummy cycle can occur directly after power is supplied to
the ADC. If the first valid conversion is then performed
directly after the dummy conversion, care must be taken to
ensure that adequate acquisition time has been allowed.
As mentioned earlier, when powering up from the power-
down mode, the part will return to track upon the first
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