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參數(shù)資料
| 型號： | AD744JR-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | Precision, 500 ns Settling BiFET Op Amp |
| 中文描述： | OP-AMP, 2000 uV OFFSET-MAX, 13 MHz BAND WIDTH, PDSO8 |
| 封裝： | PLASTIC, SOIC-8 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AD744JR-REEL |
REV. PrF
PRELIMINARY TECHNICAL DATA
AD7450A/AD7440
–6–
Limit at T
MIN
, T
MAX
Parameter
2.7V-3.6V 4.75V-5.25V
Units
Description
f
SCLK
4
10
18
16 x t
SCLK
888
25
10
18
16 x t
SCLK
888
25
kHz min
MHz max
t
CONVERT
t
SCLK
= 1/f
SCLK
ns max
ns min
t
QUIET
Minimum Quiet Time between the End of a Serial Read and the
Next Falling Edge of
CS
Minimum
CS
Pulsewidth
CS
falling Edge to SCLK Falling Edge Setup Time
Delay from
CS
Falling Edge Until SDATA 3-State Disabled
Data Access Time After SCLK Falling Edge
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Edge to Data Valid Hold Time
SCLK Falling Edge to SDATA 3-State Enabled
SCLK Falling Edge to SDATA 3-State Enabled
Power-Up Time from Full Power-Down
t
1
t
2
t
35
t
45
t
5
t
6
t
7
t
86
10
10
20
40
0.4 t
SCLK
0.4 t
SCLK
10
10
35
1
10
10
20
40
0.4 t
SCLK
0.4 t
SCLK
10
10
35
1
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μs max
t
POWER-UP7
NOTES
1
Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 Volts.
2
See Figure 1, Figure 2 and the ‘Serial Interface’ section.
3
Common Mode Voltage.
4
Mark/Space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V and time for
an output to cross 0.4 V or 2.0 V for V
= 3 V.
6
t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured num-
ber is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the
timing characteristics is the true bus relinquish time of the part and is independent of the bus loading.
7
See ‘Power-up Time’ Section.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1,2
( V
DD
= 2.7V to 3.6V, f
SCLK
= 18MHz, f
S
= 1MSPS, V
REF
= 2.0 V;
V
DD
= 4.75V to 5.25V, f
SCLK
= 18MHz, f
S
= 1MSPS, V
REF
= 2.5 V;
V
CM 3
= V
REF
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Figure 1. AD7450A Serial Interface Timing Diagram
Figure 2. AD7440 Serial Interface Timing Diagram
1
2
3
4
5
13
16
15
14
t
3
0
0
0
0
DB11
DB10
DB2
DB1
DB0
t2
4 LEADING ZERO’S
3
-
S
T
ATE
t4
t6
t5
t7
t8
tQUIET
CONVERT
t
SCLK
SDATA
t1
1
2
3
4
5
13
16
15
14
t3
0
0
0
0
DB9
DB8
DB0
0
0
t2
4 LEADING ZERO’S
3-STATE
t4
t6
t5
t7
t8
tQUIET
CONVERT
t
B
SCLK
SDATA
t1
2 TRAILING ZEROS
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| AD744K | 制造商:Analog Devices 功能描述: |
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