參數(shù)資料
型號(hào)： AD744JR-REEL
廠商： ANALOG DEVICES INC
元件分類： 運(yùn)動(dòng)控制電子
英文描述： Precision, 500 ns Settling BiFET Op Amp
中文描述： OP-AMP, 2000 uV OFFSET-MAX, 13 MHz BAND WIDTH, PDSO8
封裝： PLASTIC, SOIC-8
文件頁(yè)數(shù)： 13/24頁(yè)
文件大?。?/td> 914K
代理商： AD744JR-REEL
REV. PrF
PRELIMINARY TECHNICAL DATA
–13–
AD7450A/AD7440
CIRCUIT INFORMATION
The AD7450A/AD7440 are 12- and 10- bit, fast, low
power, single supply, successive approximation analog-to-
digital converters (ADC). They can operate with a 5 V
and 3 V power supply and are capable of throughput rates
up to 1MSPS when supplied with an 18MHz SCLK. They
require an external reference to be applied to the V
REF
pin,
with the value of the reference chosen depending on the
power supply and what suits the application.
The AD7450A/AD7440 requires an external reference.
When operated with a 5 V supply, the maximum reference
that can be applied is 3.5 V and when operated with a 3 V
supply, the maximum reference that can be applied is 2.2
V. (See ‘Reference Section’).
The AD7450A/AD7440 has an on-chip differential track
and hold amplifier, a successive approximation (SAR)
ADC and a serial interface, housed in either an 8-lead
SOT-23 or MSOP package. The serial clock input ac-
cesses data from the part and also provides the clock source
for the successive-approximation ADC. The AD7450A/
AD7440 feature a power-down option for reduced power
consumption between conversions. The power-down fea-
ture is implemented across the standard serial interface as
described in the ‘Modes of Operation’ section.
CONVERTER OPERATION
The AD7450A/AD7440 is a successive approximation
ADC based around two capacitive DACs. Figures 4 and 5
show simplified schematics of the ADC in Acquisition and
Conversion phase respectively. The ADC comprises of
Control Logic, a SAR and two capacitive DACs. In fig-
ure 4 (acquisition phase), SW3 is closed and SW1 and
SW2 are in position A, the comparator is held in a bal-
anced condition and the sampling capacitor arrays acquire
the differential signal on the input
SW3
VIN+
VIN-
SW1
SW2
Cs
Cs
A
A
B
VREF
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
COMPARATOR
B
Figure 4. ADC Acquisition Phase
When the ADC starts a conversion (figure 5), SW3 will
open and SW1 and SW2 will move to position B, causing
the comparator to become unbalanced. Both inputs are
disconnected once the conversion begins. The Control
Logic and the charge redistribution DACs are used to add
and subtract fixed amounts of charge from the sampling
capacitor arrays to bring the comparator back into a bal-
anced condition. When the comparator is rebalanced, the
conversion is complete. The Control Logic generates the
ADC’s output code. The output impedances of the
sources driving the V
IN+
and the V
IN-
pins must be
matched otherwise the two inputs will have different set-
tling times, resulting in errors.
SW3
VIN+
VIN-
SW1
SW2
Cs
Cs
A
B
A
B
VREF
CONTROL
LOGIC
CAPACITIVE
DAC
CAPACITIVE
DAC
COMPARATOR
Figure 5. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7450A/AD7440 is two’s
complement. The designed code transitions occur at suc-
cessive LSB values (i.e. 1LSB, 2LSBs, etc.). The LSB
size of the AD7450A is 2xV
REF
/4096 and the LSB size of
the AD7440 is 2xV
REF
/1024. The ideal transfer character-
istic of the AD7450A/AD7440 is shown in figure 6.
100...000
+VREF - 1LSB
100...001
100...010
111...111
000...000
000...001
011...110
011...111
-VREF + 1LSB
0LSB
A
1LSB = 2xVREF/4096 (AD7450A)
iLSB = 2xVREF/1024 (AD7440)
ANALOG INPUT
(VIN+- VIN-)
Figure 6. AD7450A/AD7440 Ideal Transfer Characteristic
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