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| 型號： | AD744AH |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | Precision, 500 ns Settling BiFET Op Amp |
| 中文描述： | OP-AMP, 2000 uV OFFSET-MAX, 13 MHz BAND WIDTH, MBCY8 |
| 封裝： | HERMETIC SEALED, METAL CAN, TO-99, 8 PIN |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 914K |
| 代理商： | AD744AH |
REV. PrF
PRELIMINARY TECHNICAL DATA
–19–
AD7450A/AD7440
Examples. To achieve 1MSPS with an 18MHz clock for
V
DD
= 3 V and 5 V, an 18 clock burst will perform the
conversion and leave enough time before the next conversion
for the acquisition and quiet time.
In applications with a slower SCLK, it may be possible to
read in data on each SCLK rising edge i.e. the first rising
edge of SCLK after the
CS
falling edge would have the
leading zero provided and the 15th SCLK edge would have
DB0 provided.
Timing Example 1
Having F
SCLK
= 18MHz and a throughput rate of
1MSPS gives a cycle time of:
1/Throughput = 1/1,000,000 = 1μs
A cycle consists of:
t
2
+ 12.5 (1/F
SCLK
) + t
ACQ
= 1μs.
Therefore if t
2
= 10ns then:
10ns + 12.5(1/18MHz) + t
ACQ
= 1μs
t
ACQ
= 296ns
This 296ns satisfies the requirement of 200ns for t
ACQ
.
From Figure 20, t
ACQ
comprises of:
2.5(1/F
SCLK
) + t
8
+ t
QUIET
where t
8
= 35ns. This allows a value of 122ns for t
QUIET
satisfying the minimum requirement of 25ns.
Timing Example 2
Having F
SCLK
= 5MHz and a throughput rate of
315kSPS gives a cycle time of :
1/Throughput = 1/315000 = 3.174μs
A cycle consists of:
t
2
+ 12.5 (1/F
SCLK
) + t
ACQ
= 3.174μs.
Therefore if t
2
is 10ns then:
10ns + 12.5(1/5MHz) + t
ACQ
= 3.174μs
t
ACQ
= 664ns
This 664ns satisfies the requirement of 200ns for t
ACQ
.
From Figure 20, t
ACQ
comprises of:
2.5(1/F
SCLK
) + t
8
+ t
QUIET
where t
8
= 35ns. This allows a value of 129ns for t
QUIET
satisfying the minimum requirement of 25ns.
As in this example and with other slower clock values, the
signal may already be acquired before the conversion is
complete but it is still necessary to leave 25ns minimum
t
QUIET
between conversions. In example 2
the signal should
be fully acquired at approximately point C in Figure 20.
MODES OF OPERATION
The mode of operation of the AD7450A/AD7440 is selected
by controlling the logic state of the
CS
signal during a
conversion. There are two possible modes of operation,
Normal Mode and Power-Down Mode. The point at which
CS
is pulled high after the conversion has been initiated will
determine whether or not the AD7450A/AD7440 will enter
the power-down mode. Similarly, if already in power-down,
CS
controls whether the devices will return to normal
operation or remain in power-down. These modes of
operation are designed to provide flexible power manage-
ment options. These options can be chosen to optimize the
power dissipation/throughput rate ratio for differing applica-
tion requirements.
Normal Mode
This mode is intended for fastest throughput rate perfor-
mance. The user does not have to worry about any
power-up times with the AD7450A/AD7440 remaining
fully powered up all the time. Figure 21 shows the gen-
eral diagram of the operation of the AD7450A/AD7440 in
this mode. The conversion is initiated on the falling edge
of
CS
as described in the ‘Serial Interface Section’. To
ensure the part remains fully powered up,
CS
must remain
low until at least 10 SCLK falling edges have elapsed after
the falling edge of
CS
.
If
CS
is brought high any time after the 10th SCLK fall-
ing edge, but before the 16th SCLK falling edge, the part
will remain powered up but the conversion will be termi-
nated and SDATA will go back into three-state. Sixteen
serial clock cycles are required to complete the conversion
and access the complete conversion result.
CS
may idle
high until the next conversion or may idle low until some-
time prior to the next conversion. Once a data transfer is
another conversion can be initiated after the quiet time,
t
QUIET
has elapsed by again bringing
CS
low.
Figure 20. Serial Interface Timing Example
1
2
3
4
5
13
16
15
14
t2
t6
t5
t8
t
QUIET
CONVERT
t
B
tACQUISITION
12.5(1/fSCLK)
1/Throughput
10ns
SCLK
C
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