AD7392/AD7393
Rev. C | Page 9 of 20
100
95
90
85
80
75
70
65
60
55
50
0
VLOGIC FROM
0V TO 3V
VLOGIC FROM
3V TO 0V
3.0
2.5
2.0
1.5
1.0
0.5
01
12
1-
0
14
VIN (V)
S
UP
P
LY
CU
RRE
N
T
(
A)
AD7392
VDD = 3V
TA = 25°C
Figure 11. Supply Current vs. Logic Input Voltage
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
17
6
5
4
3
2
01
12
1-
01
5
SUPPLY VOLTAGE (V)
T
HRE
S
HO
L
D
V
O
LT
AG
E
(
V
)
AD7392
CODE = 0xFFF
VREF = 2V
RS LOGIC VOLTAGE
VARIED
VLOGIC FROM
LOW TO HIGH
VLOGIC FROM
HIGH TO LOW
Figure 12. Logic Threshold vs. Supply Voltage
100
30
40
50
60
70
80
90
20
–55
–35
–15
5
25
45
65
85
105
125
01
12
1-
01
6
TEMPERATURE (°C)
S
UP
P
LY
CUR
RE
NT
(
A)
VDD = 5V, VLOGIC = 0V
VDD = 3.6V, VLOGIC = 2.4V
VDD = 3V, VLOGIC = 0V
AD7392
SAMPLE SIZE = 300 UNITS
Figure 13. Supply Current vs. Temperature
1000
800
600
400
200
0
1k
10k
100k
1M
10M
01
12
1-
01
7
CLOCK FREQUENCY (Hz)
S
UP
P
LY
CUR
RE
NT
(
A)
a
b
c
d
a. VDD = 5.5V, CODE = 0x155
b. VDD = 5.5V, CODE = 0x3FF
c. VDD = 2.7V, CODE = 0x155
d. VDD = 2.7V, CODE = 0x355
AD7392
VLOGIC = 0V TO VDD TO 0V
VREF = 2.5V
TA = 25°C
Figure 14. Supply Current vs. Clock Frequency
60
50
40
30
20
10
0
10
100
1k
10k
01
12
1-
01
8
FREQUENCY (Hz)
P
S
RR
(
d
B)
TA = 25°C
VDD = 5V ± 5%
VDD = 3V ± 5%
Figure 15. Power Supply Rejection Ratio vs. Frequency
40
30
20
10
0
05
4
3
2
1
01
12
1-
01
9
VOUT (V)
I OU
T
(m
A
)
VDD = 5V
VREF = 3V
CODE = 0x000
Figure 16. IOUT at Zero Scale vs. VOUT