AVCC = DV
參數(shù)資料
型號(hào)： AD7366BRUZ-RL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 28/29頁(yè)
文件大小： 0K
描述： IC ADC 12BIT SAR 1MSPS 24TSSOP
設(shè)計(jì)資源： Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
標(biāo)準(zhǔn)包裝： 1,000
系列： iCMOS®
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 88.8mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 4 個(gè)單端，單極；4 個(gè)單端，雙極
配用： EVAL-AD7366CBZ-ND - BOARD EVALUATION FOR AD7366
AD7366/AD7367
Rev. D | Page 7 of 28
TIMING SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V, VDD = 11.5 V to 16.5 V, VSS = 16.5 V to 11.5 V, VDRIVE = 2.7 V to 5.25 V, TA = 40°C to +85°C,
unless otherwise noted.1
Table 4.
Parameter
Limit at T
MIN, TMAX
Unit
Test Conditions/Comments
2.7 V ≤ V
DRIVE < 4.75 V
4.75 V ≤ V
DRIVE ≤ 5.25 V
t
CONVERT
Conversion time, internal clock; CNVST falling edge to
BUSY falling edge
680
ns max
AD7367
610
ns max
AD7366
f
SCLK
10
kHz min
Frequency of serial read clock
35
48
MHz max
t
QUIET
30
ns min
Minimum quiet time required between the end of serial
read and the start of the next conversion
t
1
10
ns min
Minimum CNVST low pulse
t
2
40
ns min
CNVST falling edge to BUSY rising edge
t
3
0
ns min
BUSY falling edge to MSB, valid when CS is low for t4 prior
to BUSY going low
t
4
10
ns max
Delay from CS falling edge until Pin 1 (DOUTA) and Pin 23
(D
OUTB) are three-state disabled
20
14
ns max
Data access time after SCLK falling edge
t
6
7
ns min
SCLK to data valid hold time
t
7
0.3 × t
SCLK
0.3 × t
SCLK
ns min
SCLK low pulse width
t
8
0.3 × t
SCLK
0.3 × t
SCLK
ns min
SCLK high pulse width
t
9
10
ns max
CS rising edge to DOUTA, DOUTB, high impedance
t
POWER-UP
70
s max
Power-up time from shutdown mode; time required
between CNVST rising edge and CNVST falling edge
1 Sample tested during initial release to ensure compliance. All input signals are specified with t
R = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
All timing specifications are with a 25 pF load capacitance. With a load capacitance greater than 25 pF, a digital buffer or latch must be used. See the Terminology
2 The time required for the output to cross is 0.4 V or 2.4 V.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD7367 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:True Bipolar Input, Dual 1 レs, 12-/14-Bit, 2-Channel SAR ADCs
AD7367-5 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:True Bipolar Input, Dual 1 レs, 12-/14-Bit, 2-Channel SAR ADCs
AD7367-5ARUZ 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:1 MSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
AD7367-5ARUZ-REEL7 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:1 MSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
AD7367-5BRUZ 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:1 MSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
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