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參數(shù)資料
| 型號： | AD7366BRUZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/29頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT SAR 1MSPS 24TSSOP |
| 設(shè)計資源： | Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042) |
| 標準包裝： | 1,000 |
| 系列： | iCMOS® |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 88.8mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極 |
| 配用： | EVAL-AD7366CBZ-ND - BOARD EVALUATION FOR AD7366 |
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AD7366/AD7367
Rev. D | Page 22 of 28
SERIAL INTERFACE
Figure 25 and Figure 26 show the detailed timing diagram for
serial interfacing to the AD7366 and the AD7367. On the
falling edge of CNVST, the AD7366/AD7367 simultaneously
convert the selected channels. These conversions are performed
using the on-chip oscillator. After the falling edge of CNVST,
the BUSY signal goes high, indicating that the conversion has
started. The BUSY signal returns low when the conversion has
been completed. The data can now be read from the
DOUT pins.
The CS and SCLK signals are required to transfer data from the
AD7366/AD7367. The AD7366/AD7367 have two output pins
corresponding to each ADC. Data can be read from the AD7366/
AD7367 using both DOUTA and DOUTB. Alternatively, a single
output pin of the user’s choice can be used. The SCLK input
signal provides the clock source for the serial interface. The CS
goes low to access data from the AD7366/AD7367. The falling
edge of CS takes the bus out of three-state and clocks out the
MSB of the conversion result. The data stream consists of
12 bits of data for the AD7366 and 14 bits of data for the
AD7367, MSB first. The first bit of the conversion result is
valid on the first SCLK falling edge after the CS falling edge.
The subsequent 11/13 bits of data for the AD7366/AD7367,
respectively, are clocked out on the falling edge of the SCLK
signal. A minimum of 12 clock pulses must be provided to the
AD7366 to access each conversion result, and a minimum of
14 clock pulses must be provided to the AD7367 to access the
conversion result. Figure 25 shows how a 12 SCLK read is used
to access the conversion results for the AD7366, and Figure 26
illustrates the case for the AD7367 with a 14 SCLK read.
On the rising edge of CS the conversion is terminated and
DOUTA and DOUTB return to three-state. If CS is not brought
high, but is instead held low for an additional 14 SCLK cycles
the data from the other DOUT pin follows on the selected
DOUT pin. Note, the second serial result from the AD7366 is
preceeded by two zeros. See Figure 27 and Figure 28, where
DOUTA is shown. In this case, the DOUT line in use returns to
three-state on the rising edge of CS.
If the falling edge of SCLK coincides with the falling edge of CS,
the falling edge of SCLK is not acknowledged by the AD7366/
AD7367, and the next falling edge of SCLK is the first one
registered after the falling edge of CS.
The CS pin can be brought low before the BUSY signal goes
low, indicating the end of a conversion. When CS is at a logic
low state, the data bus is brought out of three-state. This feature
can be used to ensure that the MSB is valid on the falling edge
of BUSY by bringing CS low a minimum of t4 before the BUSY
signal goes low. The dotted CS
illustrates this feature.
Alternatively, the CS pin can be tied to a low logic state continu-
ously. In this case, the DOUT pins never enter three-state and the
data bus is continuously active. Under these conditions, the MSB
of the conversion result for the AD7366/AD7367 is available on
the falling edge of the BUSY signal. The next most significant
bit is available on the first SCLK falling edge after the BUSY
signal has gone low. This mode of operation enables the user to
read the MSB as soon as it is made available by the converter.
DOUTA
DOUTB
THREE-
STATE
THREE-STATE
CS
SCLK
1
5
12
2
3
4
DB10
DB11
DB9
DB8
DB2
DB1
DB0
t5
t6
t8
t4
t7
t9
06703-
027
Figure 25. Serial Interface Timing Diagram for the AD7366
DOUTA
DOUTB THREE-
STATE
THREE-STATE
CS
SCLK
1
5
14
2
3
4
DB12
DB13
DB11
DB10
DB2
DB1
DB0
t5
t6
t8
t4
t7
t9
06703-
028
Figure 26. Serial Interface Timing Diagram for the AD7367
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7367 | 制造商:AD 制造商全稱:Analog Devices 功能描述:True Bipolar Input, Dual 1 レs, 12-/14-Bit, 2-Channel SAR ADCs |
| AD7367-5 | 制造商:AD 制造商全稱:Analog Devices 功能描述:True Bipolar Input, Dual 1 レs, 12-/14-Bit, 2-Channel SAR ADCs |
| AD7367-5ARUZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 MSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC |
| AD7367-5ARUZ-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 MSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC |
| AD7367-5BRUZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 MSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC |
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